IMX8 RGMII : ENET_REF_CLK and ENET RESET

[enoch_arthur]

Hi , I am trying implement a phy-less Ethernet connection between an IMX 8 and an FPGA and not quite sure which signals I need to ultimately get a working interface. This is the reference design recommended by NXP.

I am guessing the GTX_clk125 is the enet_ref_clk which I have seen in the likes of the imx6. I have however not seen any such clock input in the IMX8. so where do I connect this GTX_clk125? 

There is an enet_phy_ref_clk_root output (GPIO1_io09) but this is not used for ethernet on the imx8 demo board.

There is also enet_nRST going to the GPIO1_io09 of the imx8 demo board from the phy. Do I have to feed an reset signal from the FPGA to this pin as well?

Any help will be deeply appreciated.

Thanks.

[enoch_arthur]

Hi Igor,

Thanks for the reply. Very good info on the enet_nRST but still not very clear with the enet_ref_clk.

 Are you saying that the source of the  ENET1_RGMII_TXC  can be from either internal (Enet1_tx_clk_sel = 0) or an external enet_ref_clk (Enet1_tx_clk_sel = 1 ) if this is the case, which pin do I connect this external enet_ref_clk ?

If that's not the case, what is this enet_ref_clk used for and which pin is it? I thought you only need the ENET1_RGMII_TXC and ENET1_RGMII_RXC clocks for transmit and receive respectively.

[igorpadykov]

Hi Enoch

> Are you saying that the source of the  ENET1_RGMII_TXC  can be
>from either internal (Enet1_tx_clk_sel = 0) or an external enet_ref_clk (Enet1_tx_clk_sel = 1 )

yes

>if this is the case, which pin do I connect this external enet_ref_clk ?

ENET1_RGMII_TXC signal, pad ENET_TXC as described in sect.8.1.1.1 Muxing Options

i.MX 8M Dual/8M QuadLite/8M Quad Applications Processors Reference Manua

Best regards
igor

[enoch_arthur]

Hi Igor,

Thanks again and sorry for still not understanding. ENET1_RGMII_TXC from the data sheet page 47 is an output port . Clock signal that clocks the transmit data to the phy, right? 

From our earlier discussion, we worked out that the source for this output port ( ENET1_RGMII_TXC) can be internally generated or from yet another port (input port)  if I choose Enet1_tx_clk_sel = 1.

My question is which input port can this external clock be put so it can be outputted on  ENET1_RGMII_TXC for Enet1_tx_clk_sel = 1. I hope I am clear now?  The clock can be internally generated from the crystal or feed in from another port(which I think is called  enet_ref_clk) . 

This then get outputted onto ENET1_RGMII_TXC. hope tht's the case

[igorpadykov]

Hi Enoch

>My question is which input port can this external clock be put so it can be outputted on  ENET1_RGMII_TXC >for Enet1_tx_clk_sel = 1. I hope I am clear now?

it is ENET1_RGMII_TXC signal, pad ENET_TXC as described in sect.8.1.1.1 Muxing Options

i.MX 8M Dual/8M QuadLite/8M Quad Applications Processors Reference Manua

It can be input or output depending on bit ENET1_TX_CLK_SEL IOMUX GPR1  register.

Best regards
igor

[enoch_arthur]

Ok so if the ENET1_RGMII_TXC is configured as the input to receive the reference clock, which port will the transmit clock going to the phy  comes from? We have the txdata and transmit control signals going from the imx8 to the phy, there is a clock that goes with it, right? which output port will that come from? Surely if the ENET1_RGMII_TXC is configured as an input to receive the ref clock, it cannot at the same time output the tx clock to the phy . 

[igorpadykov]

>Ok so if the ENET1_RGMII_TXC is configured as the input to receive the reference clock,

>which port will the transmit clock going to the phy  comes from?

i.MX8M pad ENET_TXC can be input or output depending on bit ENET1_TX_CLK_SEL IOMUX GPR1  register,

but not both. So you can have clock generated by i.MX8M and provided to fpga, or clock generated by fpga

and provided to i.MX8M (pad ENET_TXC configured as input).

[enoch_arthur]

Thanks for the reply Igor.

Are you saying when data is being sent from processor to the FPGA, the clock can go in the opposite direction(FPGA to processor)?

What I know is the clock always go where the data is going. So for an ethernet interface , the are 2 interfaces, receive and transmit. From the processor's view,  Data going from processor to the FPGA is sent on the transmit side (txdata , tx_ctrl and tx_clock) all going from processor to the FPGA.

On the receive side(rxdata , rx_ctrl and rx_clock) data moves from FPGA to processor. It's hard to understand that when data is going from processor to FPGA, the clock which needs to go with it comes from the receiver. Unless there is an independent clock that clocks both the transmit end and the receive end. Is that the case?

[igorpadykov]

Hi Enoch

>Are you saying when data is being sent from processor to the FPGA, the clock can

>go in the opposite direction(FPGA to processor)?

yes, with ENET1_RGMII_TXC is configured as the input to receive the external reference clock.

Best regards
igor

[igorpadykov]

Hi Enoch

ENET1_RGMII_TXC clock input can be configured with bit ENET1_TX_CLK_SEL IOMUX GPR1

 register, described in sect.8.2.4.2 GPR1 General Purpose Register (IOMUXC_GPR_GPR1)

i.MX 8M Dual/8M QuadLite/8M Quad Applications Processors Reference Manua

enet_nRST is used for resetting phy, it is output from processor, any processor gpio can be used for that.

Best regards
igor
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