IMX8 Nano custom board DDR calibration(Waiting for the target board boot...)

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IMX8 Nano custom board DDR calibration(Waiting for the target board boot...)

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love1ymano
Contributor II

Hi,

We are developing a custom board based on IMX8 Nano processor. We had taken IMX8 Nano EVK board as reference. Below are some the of main changes in our custom board compare to EVK

1) PMIC - PCA9450B

2) Debug UART - Taken out from SAI3_TXFS, SAI3_TXC lines(Muxed).

3) DDR - DDR3L (MT41K256M16TW-107)

Generated DDR stress test script using preliminary_MX8M_Nano_DDR3L_RPA_v1.xlsx file. Made below changes in UART mux & PMIC configuration in according to our custom board.

################step 0: configure debug uart port. Assumes use of UART IO Pads. #####
##### If using non-UART pads (i.e. using other pads to mux out the UART signals), #####
##### then it is up to the user to overwrite the following IO register settings #####
memory set 0x303301D8 32 0x00000100 #IOMUXC_SW_MUX_SAI3_TXFS (Select UART 2 mux)
memory set 0x303301DC 32 0x00000100 #IOMUXC_SW_MUX_SAI3_TXC
memory set 0x30330440 32 0x0000000E #IOMUXC_SW_PAD_SAI3_TXFS
memory set 0x30330444 32 0x0000000E #IOMUXC_SW_PAD_SAI3_TXC
memory set 0x303304FC 32 0x00000010 #IOMUXC_SW_MUX_UART2_SEL_RXD
sysparam set debug_uart 1 #UART index from 0 ('0' = UART1, '1' = UART2, '2' = UART3, '3' = UART4)
sysparam set fw_version 1 #Firmware Selection: '0' for FW201709, '1' for FW201810

##### PMIC DDR voltage configuration #####
memory set 0x3033022C 32 0x00000000 #IOMUXC_SW_MUX_I2C4_SCL
memory set 0x30330230 32 0x00000000 #IOMUXC_SW_MUX_I2C4_SDA
memory set 0x30330494 32 0x000000C6 #IOMUXC_SW_PAD_I2C4_SCL
memory set 0x30330498 32 0x000000C6 #IOMUXC_SW_PAD_I2C4_SDA

sysparam set pmic_cfg 0x0325 # PMIC_ADDR[0:7] = 0x25, I2C_BUS[8:15] = 3(I2C4)
sysparam set pmic_cfg 0x290C
sysparam set pmic_cfg 0x1C11
sysparam set pmic_cfg 0x1412
sysparam set pmic_cfg 0x5910
sysparam set pmic_cfg 0x1E1E
sysparam set pmic_cfg 0xC022
sysparam set pmic_cfg 0x4424
sysparam set pmic_cfg 0xA108



################step 1: DDR clock configuration################
memory set 0x30391000 32 0x8F00003F #SRC_DDRC_RCR_ADDR: assert [0]ddr1_preset_n, [1]ddr1_core_reset_n, [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n, [4]src_system_rst_b!
memory set 0x30391000 32 0x8F00000F #SRC_DDRC_RCR_ADDR: deassert [4]src_system_rst_b!

memory set 0x3038A088 32 0x07070000 #DRAM_APB_CLK_ROOT_CLR
memory set 0x3038A084 32 0x04030000 #DRAM_APB_CLK_ROOT_SET, dram_apb_clk_root set to source 4 --800MHz/4

#disable the clock gating
memory set 0x303A00EC 32 0x0000FFFF #PGC_CPU_MAPPING
memory setbit 0x303A00F8 32 0x20 #GPC_PU_PGC_SW_PUP_REQ: DDR1_SW_PUP_REQ=1

memory set 0x30391004 32 0x8F000000 #SRC_DDRC_RCR_ADDR

#DRAM_PLL_CONFIG
# The RPA provides the DRAM_PLL_FDIV_CTL0 register (0x30360054) setting for 800Mhz (0x12C091)
# For frequencies other than 800Mhz, it is up to the user to create the appropriate register setting for the desired frequency.
# Formula is DDR_freq = [(24MHz x pll_main_div)/(pll_pre_div x 2^pll_post_div)] x 2
memory set 0x30360054 32 0x12C091 #DRAM_PLL_FDIV_CTL0: For 800MHz, pll_main_div = 300, pll_pre_div = 9, pll_post_div = 1
memory set 0x30360058 32 0x00000000 #DRAM_PLL_FDIV_CTL1: pll_dsm=0
memory setbit 0x30360050 32 0x200 #DRAM_PLL_GNRL_CTL: pll_rst = 1
memory clrbit 0x30360050 32 0x10 #DRAM_PLL_GNRL_CTL: pll_bypass = 0
memory chkbit1 0x30360050 32 0x80000000 #DRAM_PLL_GNRL_CTL: check pll_lock=1?

memory set 0x30391000 32 0x8F000006

################step2: DDRC configuration ################
memory set 0x3d400304 32 0x00000001 #DDRC_DBG1: dis_dq=1, indicates no reads or writes are issued to SDRAM
memory set 0x3d400030 32 0x00000020 #DDRC_PWRCTL: selfref_sw=1, entry self refresh
memory set 0x3D400000 32 0x81040001 #DDRC_MSTR
memory set 0x3D400050 32 0x00210070 #DDRC_RFSHCTL0
memory set 0x3D400064 32 0x00610068 #DDRC_RFSHTMG

memory set 0x3D4000D0 32 0xC00200C5 #DDRC_INIT0
memory set 0x3D4000D4 32 0x0001000B #DDRC_INIT1
memory set 0x3D4000DC 32 0x1D700004 #DDRC_INIT3
memory set 0x3D4000E0 32 0x00180000 #DDRC_INIT4
memory set 0x3D4000E4 32 0x00090000 #DDRC_INIT5
memory set 0x3D4000F0 32 0x00000000 #DDRC_DIMMCTL:[1] dimm_addr_mirr_en, it will effect the MRS if use umctl2 to initi dram.
memory set 0x3D4000F4 32 0x00000EE5 #DDRC_RANKCTL

memory set 0x3D400100 32 0x0C101B0E #DDRC_DRAMTMG0
memory set 0x3D400104 32 0x00030314 #DDRC_DRAMTMG1
memory set 0x3D400108 32 0x04060509 #DDRC_DRAMTMG2
memory set 0x3D40010C 32 0x00002006 #DDRC_DRAMTMG3
memory set 0x3D400110 32 0x06020306 #DDRC_DRAMTMG4
memory set 0x3D400114 32 0x04040302 #DDRC_DRAMTMG5
memory set 0x3D400120 32 0x00000909 #DDRC_DRAMTMG8

memory set 0x3D400180 32 0x40800020 #DDRC_ZQCTL0
memory set 0x3D400184 32 0x0000C350 #DDRC_ZQCTL1

memory set 0x3D400190 32 0x03868203 #DDRC_DFITMG0
memory set 0x3D400194 32 0x00020303 #DDRC_DFITMG1
memory set 0x3D4001B4 32 0x00000603 #DDRC_DFITMG2
memory set 0x3D400198 32 0x07000000 #DDRC_DFILPCFG0
memory set 0x3D4001B0 32 0x00000011 #DDRC_DFIMISC
memory set 0x3D4001A0 32 0x00400018 #DDRC_DFIUPD0
memory set 0x3D4001A4 32 0x0005003C #DDRC_DFIUPD1
memory set 0x3D4001A8 32 0x80000000 #DDRC_DFIUPD2

memory set 0x3D4001C4 32 0x00000000 #DDRC_DFI_PHYMSTR

memory set 0x3D400200 32 0x0000001F #DDRC_ADDRMAP0
memory set 0x3D400204 32 0x00080808 #DDRC_ADDRMAP1
memory set 0x3D400208 32 0x00000000 #DDRC_ADDRMAP2
memory set 0x3D40020C 32 0x00000000 #DDRC_ADDRMAP3
memory set 0x3D400210 32 0x00001F1F #DDRC_ADDRMAP4
memory set 0x3D400214 32 0x07070707 #DDRC_ADDRMAP5
memory set 0x3D400218 32 0x0F070707 #DDRC_ADDRMAP6

memory set 0x3D400240 32 0x0600060C #DDRC_ODTCFG
memory set 0x3D400244 32 0x00001323 #DDRC_ODTMAP

#performance optimization
memory set 0x3D400400 32 0x00000100 #DDRC_PCCFG
memory set 0x3D400250 32 0x7AB50B07 #DDRC_SCHED
memory set 0x3D400254 32 0x00000022 #DDRC_SCHED1
memory set 0x3D40025C 32 0x7B00665E #DDRC_PERFHPR1
memory set 0x3D400264 32 0x2B00C4E1 #DDRC_PERFLPR1
memory set 0x3D40026C 32 0xB700C9FE #DDRC_PERFWR1
memory set 0x3D400300 32 0x00000017 #DDRC_DBG0
memory set 0x3D40036C 32 0x00010000 #DDRC_POISONCFG
memory set 0x3D400404 32 0x00003051 #DDRC_PCFGR_0
memory set 0x3D400408 32 0x000061D2 #DDRC_PCFGW_0
memory set 0x3D400494 32 0x02100B04 #DDRC_PCFGQOS0_0
memory set 0x3D400498 32 0x003F0353 #DDRC_PCFGQOS1_0
memory set 0x3D40049C 32 0x00000002 #DDRC_PCFGWQOS0_0
memory set 0x3D4004A0 32 0x000005FD #DDRC_PCFGWQOS1_0

#RESET DDRC
memory set 0x30391000 32 0x8F000004 #SRC_DDRC_RCR_ADDR
memory set 0x30391000 32 0x8F000000 #SRC_DDRC_RCR_ADDR
memory set 0x3d400304 32 0x00000000 #DDRC_DBG1
memory set 0x3d400060 32 0x00000001 #DDRC_RFSHCTL3---dis_auto_refresh
memory set 0x3d400320 32 0x00000000 #DDRC_SWCTL
memory set 0x3d4001b0 32 0x00000010 #DDRC_DDR_DFIMISC
memory set 0x3d400320 32 0x00000001 #DDRC_SWCTL

#########################
# DDR parameter settings
#########################

ddrparam set dram_type 1 #DDR4=0,DDR3=1,LPDDR4=2,LPDDR3=3,DDR5=4

ddrparam set num_pstat 1

ddrparam set data_width 16 #16bit or 32bit only

ddrparam set PhyVref 0x40 # Initial VREF value

#### DDR frequency point0 #####
ddrparam set frequency0 800
ddrparam set pllbypass0 0
freq0 set 0x3038A088 32 0x07070000 #CCM_TARGET_ROOT_CLR(DRAM_APB_CLK_ROOT)
freq0 set 0x3038A084 32 0x04030000 #CCM_TARGET_ROOT_SET(DRAM_APB_CLK_ROOT):MUX=4(system_pll1_800M_clk), PRE_PODF=3 //DRAM_APB_CLK=800/4=200MHz
freq0 set 0x303A00EC 32 0x0000FFFF #PGC_CPU_MAPPING,disable the clock gating
freq0 setbit 0x303A00F8 32 0x20 #GPC_PU_PGC_SW_PUP_REQ: DDR1_SW_PUP_REQ=1
freq0 set 0x30360054 32 0x12C091 #DRAM_PLL_FDIV_CTL0:pll_main_div = 300, pll_pre_div = 9, pll_post_div = 1
freq0 set 0x30360058 32 0x00000000 #DRAM_PLL_FDIV_CTL1: pll_dsm=0
freq0 setbit 0x30360050 32 0x200 #DRAM_PLL_GNRL_CTL: pll_rst = 1
freq0 clrbit 0x30360050 32 0x10 #DRAM_PLL_GNRL_CTL: pll_bypass = 0
freq0 chkbit1 0x30360050 32 0x80000000 #DRAM_PLL_GNRL_CTL: check pll_lock=1?
freq0 set 0x30389808 32 0x01000000 #CCM_TARGET_ROOT_CLR(DRAM_SEL): clear DRAM PLL bypass bit24

ddrparam set csPresent 0x1 #Indicates presence of DRAM at each chip select for PHY.
#If the bit is set to 1, the CS is connected to DRAM.
#If the bit is set to 0, the CS is not connected to DRAM.
#Set CsPresent[0] = 1 (if CS0 is populated with DRAM)
#Set CsPresent[1] = 1 (if CS1 is populated with DRAM)
#Set CsPresent[7:2] = 0 (Reserved; must be programmed to 0)

ddrparam set rdODT0 2
ddrparam set rdODT1 1
ddrparam set rdODT2 0
ddrparam set rdODT3 0

ddrparam set wrODT0 3
ddrparam set wrODT1 3
ddrparam set wrODT2 0
ddrparam set wrODT3 0

ddrparam set addrMirror 0x0 # Corresponds to CS[3:0]
# 1 = Address Mirror.
# 0 = No Address Mirror.

# The following is to configure the recommended training, it is strongly recommended not to change this
ddrparam set TrainCtrl0 0x031f #TrainCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.

# The following is for internal factory use, it is strongly recommended not to change this
ddrparam set TrainInfo 0xC8 #0x05 = Detailed debug (e.g. eys delays)

ddrparam set MR0 0x1D70
ddrparam set MR1 0x0004
ddrparam set MR2 0x0018

ddrparam set ATxImpedance 40
ddrparam set ODTImpedance 60
ddrparam set TxImpedance 40

ddrparam set extCalRes 0x00
ddrparam set WDQSExt 0x00

ddrparam set SlewRiseDQ 0x0f
ddrparam set SlewFallDQ 0x0f
ddrparam set SlewFallAC 0x0f
ddrparam set SlewRiseAC 0x0f

ddrparam set CaliInterval 0x09
ddrparam set CaliOnce 0x00

Then I run Mscale DDR tool, I got the below output and it get struck at "Waiting for the target board boot..."


love1ymano_1-1603083888923.png

 

 

 

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi love1ymano

 

usually "Waiting for the target board boot..." happens due to wrong UART configuration,

in particular UART RX path.

Also recommended to check usb circuit  and look in host computer

Device Manager for “HID-compliant device” or “USB Input Device”.

Follow usb guidelines provided in

i.MX 8M Nano Hardware Developer’s Guide

 

Best regards
igor

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