IMX7s SAI mclk clock source

[jensalsig]

Hi

I'm trying to get the the a SAI working under Linux 4.9.47. The SAI must be master (generate mclk, bclk and frame sync). The mclk must be 24.576 MHz, the blck must be  3.072MHz and the frame sync must be 48kHz.

My problem is that  I can't set configure the clock source to the SAI to any other value than 24MHz. 

I do my testing wtih "speaker-test --format S32_LE". I can measure the the mclk on the mclk pad but it is 24MHz. It seems that everything is working but with the wrong clock source. 

Questions:

1) Which clock source is used for the SAI1? IMX7D_SAI1_ROOT_CLK? IMX7D_AUDIO_MCLK_ROOT_CLK? Or...?

2) How do I configure it?

The datasheet isn't very clear regarding this.

Best regards

Jens Alsig

Device tree sniplets:

codec1: codec1 {
 compatible = "linux,snd-soc-dummy";
 #sound-dai-cells = <0>;
 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>,
 <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
 assigned-clock-rates = <0>, <24576000>;
 status = "okay";
 };

sound {
 compatible = "simple-audio-card";
 simple-audio-card,name = "sai_1";
 simple-audio-card,format = "i2s";
 simple-audio-card,bitclock-master = <&dailink1_master>;
 simple-audio-card,frame-master = <&dailink1_master>;
 simple-audio-card,mclk-fs = <512>;
 dailink1_master: simple-audio-card,cpu {
 sound-dai = <&sai1>;
 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; 
 };
simple-audio-card,codec {
 sound-dai = <&codec1>;

};
 };

&sai1 {
 pinctrl-names = "default";
 pinctrl-0 = <&pinctrl_sai1>;
 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
 <&clks IMX7D_SAI1_ROOT_CLK>;
 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 
 assigned-clock-rates = <0>,<24576000>;
 fsl,sai-mclk-direction-output;
 fsl,sai-synchronous-rx;
 status = "okay";
};‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

From the kernel the following clocks are configured:

root@morris:~# cat /sys/kernel/debug/clk/clk_summary | grep sai
sai3_src 0 0 24000000 0 0
sai3_cg 0 0 24000000 0 0
sai3_pre_div 0 0 24000000 0 0
sai3_post_div 0 0 24000000 0 0
sai3_root_clk 0 0 24000000 0 0
sai2_src 0 0 884736000 0 0
sai2_cg 0 0 884736000 0 0
sai2_pre_div 0 0 884736000 0 0
sai2_post_div 0 0 24576000 0 0
sai2_root_clk 0 0 24576000 0 0
sai1_src 0 0 884736000 0 0
sai1_cg 0 0 884736000 0 0
sai1_pre_div 0 0 884736000 0 0
sai1_post_div 0 0 24576000 0 0
sai1_root_clk 0 0 24576000 0 0
sai3_ipg_clk 0 0 0 0 0
sai2_ipg_clk 0 1 0 0 0
sai1_ipg_clk 0 1 0 0 0
root@morris:~# cat /sys/kernel/debug/clk/clk_summary | grep audio_mclk
audio_mclk_src 0 0 884736000 0 0
audio_mclk_cg 0 0 884736000 0 0
audio_mclk_pre_div 0 0 884736000 0 0
audio_mclk_post_div 0 0 24576000 0 0
audio_mclk_root_clk 0 0 24576000 0 0‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

[igorpadykov]

Hi  Jens

it is IMX7D_AUDIO_MCLK_ROOT_CLK
clock may be adjusted using common linux framework guidelines
described in linux documentation like
https://www.kernel.org/doc/Documentation/clk.txt
http://elinux.org/images/b/b8/Elc2013_Clement.pdf
https://community.nxp.com/thread/455121 

Best regards
igor
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[jensalsig]

Hi Igor

Thanks for your response.

it is IMX7D_AUDIO_MCLK_ROOT_CLK

That great! 

But if you look at the last part of my post you'll see that the IMX7D_AUDIO_MCLK_ROOT_CLK is already set to 24.576MHz.

root@morris:~# cat /sys/kernel/debug/clk/clk_summary | grep audio_mclk
audio_mclk_src 0 0 884736000 0 0
audio_mclk_cg 0 0 884736000 0 0
audio_mclk_pre_div 0 0 884736000 0 0
audio_mclk_post_div 0 0 24576000 0 0
audio_mclk_root_clk 0 0 24576000 0 0‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

I have already looked at the question that you link to, but it doesn't help me.

I am familiar with the common clock framework in Linux. 

Am I missing some detail resulting in a 24MHz clock instead of a 24.576MHz?

/Jens

[igorpadykov]

Hi Jens

one can check pre_div/post_div coefficients with jtag debugger or printf,
please look at sect.5.2.8.10 Target Register (CCM_TARGET_ROOTn) i.MX7D RM

Best regards
igor