IMX7dual with high speed ADC

[dmitriychertov]

Hello everyone!

I develope iMX7 processor based custom hardware design.

I want to connect high-speed 12-bit ADC with a parallel CMOS output to iMX7dual. The required ADC speed is 60 MSPS and higher. What is the maximum speed that the processor can support receiving 12 data bits, for example, on GPIO1 or GPIO2 and dropping it to eMMC or to RAM? What will be the maximum speed if I would use DMA or if I would use a processor core for these operations?

[art]

The GPIO ports seem to be too slow to support 60MSPS transfers. Better seems to use the Camera Sensor Interface (CSI) parallel port. For more information, please refer to the Section 13.3 "CMOS Sensor Interface (CSI)" of the i.MX7Dual Reference Manual document and to the Section 4.10.7 "CMOS sensor interface (CSI) timing parameters" of the i.MX7Dual Data Sheet document. Both documents are available on the processor's Documentation web page:

http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/i.mx-applications-process...

Have a great day,
Artur

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[dmitriychertov]

Good day, Arthur!

Thanks for the answer!

But if I correctly understand, the GPIO ports speed is based on ipg_clk_root, the maximum frequency of which is 135 MHz (page 491 Reference Manual). Then why do you say that GPIO ports are too slow for 60 MSPS transfers?

[bernhardfink · Accepted solution]

Hi Dmitriy,

if you run standard Linux then it depends from where you handle this self-defined GPIO port. From user space it simply takes time to go down and up the layers, resulting in kHz performance. If you would implement a GPIO port read driver in the Kernel, then you would end up in a lower MHz performance. If you optimize things even more (for example bare metal on the Cortex-M4) you could maybe reach a small 2-digit MHz performance, but by far not 60MHz

Now you will still ask:  Why? 

The i.MX7 includes various bus systems and timing domains with a lot of sync bridges. This is much more complex than on microcontroller architechtures like Kinetis or LPC. So most of the time when reading a GPIO value is spend in these bridges, gettings the request down and the result up. There is no way to bypass them, also not with DMA.

If you want to test it anyway by yourself, I would go with a little program on the Cortex-M4.

In a nutshell:  60MHz reads with GPIO are simply impossible, that's why Arthur recommended an interface like the CSI, which is by definition a high speed parallel input interface with a high speed connection to the bus system.

Regards,

Bernhard.

[dmitriychertov]

Hi, Bernhard,

thank you for the detailed answer! Now I understand.