It seems no relation between DRAM pad and VDD_soc, does the power block have wrong connection from VDD_soc to DRAM pad? We just want to find anything related to VDD_SOC to find out the low power mode setting root cause the difference from the Saber board.
Back to the original question, does VDD_SOC related to the DRAM pad shown in the below picture? How do we check it since we can not see relation in the schematic?
We are also investigation that the VDD_SOC power consumption behavior, please see the below two picture. The VDD_SOC is measure under u-boot. You can see there is big difference between Saber board and our board. Our SW mentioned that the setting and configuration difference is DRAM setting that Saber uses DDR3L but our board use LPDDR3. Does the DRAM configuration impact the VDD_SOC current draw? In the power rail block of the IMX7D, the VDD_SOC seems to be related to DRAM PAD. Does NXP have LPDDR3 setting sample for us to refer it?
Saber board VDD_SOC
Our board VDD_SOC
We also use VDD_SOC to supply the PCIE_VP which is used for BDSL support, is it possible to be a issue for losing power when set to low power mode?
The NVCC_1V8 also supplies to PCIE_VPH for BDSL support and the NVCC_1V8 can keep to save power without additional loss.
In An5383, it shows the VDD_SOC will reduce to 0.925V, is it wrong?
>We also use VDD_SOC to supply the PCIE_VP which is used for BDSL support, is it possible
>to be a issue for losing power when set to low power mode?
I believe yes. To be sure suggest to disconnect and connect as it is done on i.MX7D SabreSD schematic.
--It's a bad news for us that we do not have 0 ohm to the PCIE_VP. The NVCC_1v8 also connects to PCIE_VPH for the same purpose with PCIE_VP but the NVCC_1V8 can have ultra low power consumption when set to DSM. It the VDD_SOC will still have high current on DSM mode due to PCIE_VP, the NVCC_1V8 should have similar result but it does not. Do you have any idea to disable the related function used for PCIE_VP to check if we can let the PCIE_VP to stop to sink the current for VDD_soc?
1.So, the VDD_SOC power = 0.975V will not be changed whatever the M4 stay idle or active or high loading mode?
2. In Saber board, the net connect to VDDD_1p0_cap, it seems that we can not supply the VDD_soc to the PCIE_VP directly.
We use Saber board to do the experiment, we check the internal LDO VDDD_1P0_CAP power rail will be disabled and we supply external 1.0V to supply the below power rail and found the there are extra current flow to this power power rail about 20mA. The VDD_SOC on our board has 65mA, if we remove this additional 20mA, there is 44mA which is still loss in the system in suspend mode. Do you have any idea for it?
Hi Igor, we are also checking the additional power consumption on I/Os, I mean NVCC_1V8 and NVCC_3V3 to supply the NVCC_xxxx for I/O power as below:
Since we do not leave 0 ohm here but we can still measure some current on NVCC_1V8. Except these NVCC_xxx, we has disconnected the power connection for all peripheral devices. So, it seems there is still some power going into the power pins as show below when we go into DSM mode.
My question is, do we need to turn off the data bus before we excuse the DSM command? Or the DSM will auto turn off the I/O operation to save the power?
Does this power rail for NVCC_xxx have chance to consume power more than 10mA?
To turn off the integrated PMU before enter the DSM mode since they are all on in default?
