IMX7D ethernet does not work in u-boot

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IMX7D ethernet does not work in u-boot

803件の閲覧回数
sharmilad
Contributor I

Hi All,

       We are using i.Mx7D processor for one of our custom project and it is running with Linux kernel ver 5.10. We are using Micrel KSZ8041 phy and we are facing issues in bringing up the ethernet in uboot.

The mdio list commands lists the phy name but pinging is failing and we are not seeing 50Mhz clock (We are not seeing any clock).

I am copying my device tree changes here

&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec &pinctrl_fec1_reset>;
phy-reset-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>;
clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
<&clks IMX7D_ENET1_TIME_ROOT_CLK>,
<&clks IMX7D_PLL_ENET_MAIN_50M_CLK>,
<&clks IMX7D_ENET1_REF_ROOT_CLK>;

clock-names = "ipg", "ahb", "ptp", "enet_clk_ref","enet_out";
assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>;
assigned-clock-rates = <0>,<50000000>,<100000000>;
assigned-clock-rates = <50000000>;
ref-clock = <50000000>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;

ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
micrel,led-mode = <1>;
};
};
};

pinctrl_fec: fecgrp {
fsl,pins = <
MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
MX7D_PAD_SD2_WP__ENET1_MDC 0x3
MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x73
MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x73
MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x73
MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x73
MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x73
MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x73
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73
MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1 0x73
MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x00
>;
};

I am also attaching the phy signals mapping to i.Mx signals.

Please check the connection and verify the dts changes and help me to resolve the issue.

Thanks & Regards,

Sharmila

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5 返答(返信)

775件の閲覧回数
Zhiming_Liu
NXP TechSupport
NXP TechSupport

Hi @sharmilad

Please check if IMX7D_PLL_ENET_MAIN_50M_CLK exists in clk driver.

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770件の閲覧回数
sharmilad
Contributor I
Hi Qmiller,
I could see the below line in kernel clock file.
hws[IMX7D_PLL_ENET_MAIN_50M_CLK] = imx_clk_hw_gate("pll_enet_50m_clk", "pll_enet_50m", base + 0xe0, 8);
Is there anything I need to add or missing in configuring?

0 件の賞賛

766件の閲覧回数
Zhiming_Liu
NXP TechSupport
NXP TechSupport

Can you share the verison of uboot?

 

Solution1:

There is no CCM driver in uboot for i.MX7D, the compatible name is "fsl,imx7d-ccm".

You need follow other platform in this folder to port i.MX7D CCM driver https://source.codeaurora.org/external/imx/uboot-imx/tree/drivers/clk/imx?h=lf-5.15.32-2.0.0

Then the dts node can be read.

 

Solution2:

The uboot will call set_clk_enet in arch/arm/mach-imx/mx7/clock.c to set fixed clock, you can change these clock values. In this way , the dts is not work.All clocks is decided by set_clk_enet.

0 件の賞賛

761件の閲覧回数
sharmilad
Contributor I

Hi

Currently I am debugging in kernel. In kernel also I am not able to do the ping. I am attaching my kernel dts file and dmesg log.

 

&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec &pinctrl_fec1>;
/*phy-reset-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>;*/
clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
<&clks IMX7D_ENET_AXI_ROOT_CLK>,
<&clks IMX7D_ENET1_TIME_ROOT_CLK>,
<&clks IMX7D_PLL_ENET_MAIN_50M_CLK>;
clock-names = "ipg", "ahb", "ptp", "enet_clk_ref","enet_out";
assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
assigned-clock-rates = <0>,<50000000>,<100000000>;
assigned-clock-rates = <50000000>;
ref-clock = <50000000>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
clock-names = "rmii-ref";
clocks = <&clks IMX7D_ENET1_REF_ROOT_DIV>;
max-speed = <100>;
micrel,led-mode = <1>;
};
};
};

Thanks & Regards,

Sharmila D

0 件の賞賛

748件の閲覧回数
Zhiming_Liu
NXP TechSupport
NXP TechSupport

Please refer the other i.MX7D fec node to config your clocks

 

fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>,
			  <&clks IMX7D_ENET_AXI_ROOT_SRC>,
			  <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
			  <&clks IMX7D_ENET_AXI_ROOT_CLK>;
	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>,
				 <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
				 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
	assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>;
	phy-mode = "rgmii";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			reg = <0>;
		};

		ethphy1: ethernet-phy@1 {
			reg = <1>;
		};
	};
};

pinctrl_enet1: enet1grp {
			fsl,pins = <
				MX7D_PAD_GPIO1_IO10__ENET1_MDIO			0x3
				MX7D_PAD_GPIO1_IO11__ENET1_MDC			0x3
				MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC	0x1
				MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0	0x1
				MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1	0x1
				MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2	0x1
				MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3	0x1
				MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x1
				MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC	0x1
				MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0	0x1
				MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1	0x1
				MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2	0x1
				MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3	0x1
				MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x1
			>;
		};

 

 

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