I have an issue with imx6sx boting with S25FL064L (use quad io).
0a1804eb # lut command sequence
0e081200 # lut command sequence
24001e04 # lut command sequence
Verified the norflash chip registers are as expected
read control register 1: 0x02
read control register 2: 0x00
read control register 3: 0x78
read status register 1: 0x02
After power cycle, I have a BE/LE issue.
I have boards, left is a board with S25FL132K, which is working properly; right side is the same board just replaced S25FL132K with S25FL064L. Same u-boot is loaded.
The QSPI is not configured properly, the ENG_CFG should be 0 if configured properly
The lut vlaue is loaded properly
If I manually load u-boot-spl and u-boot, they both work fine.
The problem is bootrom does not load the u-boot to ram, and not execute it.
Not sure what is broken in the boot sequence. Any suggestion is apprecaited.
reason may be is that qspi configuration parameters were not updated for new qspi-nor,
described in Table 8-26. QuadSPI configuration parameters
One can try to reprogram it using for example mfg tool (script mfgtool2-yocto-mx-sabresd-qspi-nor-n25q256a.vbs, samples: qspi-nor-macronix-mx25l51245g-config, qspi-nor-micron-n25q256a-config
in folder ./files) , prepare new config file for S25FL064L
or with new uuu tool: https://github.com/NXPmicro/mfgtools
sample script example_spinor.uuu can be found in Demo Images
Thank you very much for the reply!
I have sample config for S25FL132K, and it is working on the old board. I used all those samples and figured out a new config. I uploaded it here with datasheet
Control Register 1: (Quad IO mode is enabled properly)
Control reister 2: (3-byte register mode is set)
Control register 3: (dummy cycle is 8 cycles)
Status Register 1: (write enable latch is set)
These are the right setting I need from the device.
The SEQID0 command to setup QSPI, which matches the s25fl064l datasheet:
enable quad io read, 3 bytes address will be sent in 4 pads
dummy cycle is 8 cycles, and mode uses 1 pad
Read 4 bytes
The only instruction i am not sure is 1200. I was thinking it should be 0x1202: setting mode cycle to 2; but example tells set the number of pad for mode
so can you confirm that you flashed qspi-nor with modified qspi-nor-spansion-s25fl064l-config.txt
using mfg tool?
One can write them manually from uboot, for example load them to 0x80800000, then
write to qspi-nor from 0x400 offset:
sf write 0x80800000 0x400 0x200
If the norflash content can be viewed correctly from qspi mapped address 0x60000000, it means the qspi configuration is correct, right?
How would bootrom interact with norchip ? In what mode (single/dual/quad) it copies qspi configuration from 0x400 of the norchip? How does bootrom know what mode the chip is set ?
in general one can check non-volatile registers described on p.35
like QPI, Address Length at Power-up, e.t.c.
Those info is provided in the initial post. After power cycle, the non volatile registers are as fellows:
read control register 1: 0x02 (quad mode)
read control register 2: 0x00 (3-byte address)
read control register 3: 0x78 (8 dummy cycle)
read status register 1: 0x02 (write latch enabled)
Flashed working image for S25FL132k to the new board, and it failed the exact same way:
1: QSPI MCR has wrong endiness
2: Reading norflash config/content from qspi mapped address 0x60001710, norflash content is correct.
Board still does not boot up itself.