IMX6ULL failed to set parent of clk pll1_bypass to pll1_bypass_src: -16

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IMX6ULL failed to set parent of clk pll1_bypass to pll1_bypass_src: -16

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wangxuehua
Contributor I

U-Boot 2016.03 (Oct 11 2019 - 00:33:15 -0700)

CPU: Freescale i.MX6ULL rev1.1 at 396 MHz
Reset cause: POR
Board: EPC-M6Y2C
Watchdog enabled
DRAM: 512 MiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
*** Warning - bad CRC, using default environment

In: serial
Out: serial
Err: serial
switch to partitions #0, OK
mmc1(part 0) is current device
Net: 5 not found
FEC1 MXC: board_eth_init:failed
No ethernet found.
Normal Boot
Hit 'zlg' to stop autoboot: 0
switch to partitions #0, OK
mmc1(part 0) is current device
switch to partitions #0, OK
mmc1(part 0) is current device

MMC read: dev # 1, block # 22528, count 12288 ... 12288 blocks read: OK
Booting from mmc ...

MMC read: dev # 1, block # 40960, count 768 ... 768 blocks read: OK
Saving Environment to MMC...
Writing to MMC(1)... done
Kernel image @ 0x80800000 [ 0x000000 - 0x5ee290 ]
## Flattened Device Tree blob at 83000000
Booting using the fdt blob at 0x83000000
Saving Environment to MMC...
Writing to MMC(1)... done
Using Device Tree in place at 83000000, end 8300b16b

Starting kernel ...

failed to set parent of clk pll1_bypass to pll1_bypass_src: -16

chip: MCIMX6Y2CVM08AB

could you give me some help?

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igorpadykov
NXP Employee
NXP Employee

Hi xuehua

MCIMX6Y2CVM08AB is 800MHz part and one can try Linux 4.1.15_2.0.2 Patch
i.MX 6ULL@800M Linux Binary Demo Files
i.MX Software | NXP 

Best regards
igor
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