IMX6ULL DDR calibration failed when change DDR from 512m to 1g

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IMX6ULL DDR calibration failed when change DDR from 512m to 1g

179 Views
AccuJie
Contributor III

Hi,

We have a customized IMX6ull board which changed DDR to 1GB(as4c512m16d3l-12bin).

I used ddr_stress_tester_v3.00 to calibrate DDR and got the following log info. Also, If I only changed memory size , column and row related register in .cfg file(leaves MPDGCTRL0 PHY0 //  MPRDDLCTL PHY0 // MPWRDLCTL PHY0 default) and load UBoot from sdcard. There is no output in console.  

Moreover, I also tried to boot from SPL which shown following log info in console:

U-Boot SPL 2017.03-mx6ul+g3b5f889 (Sep 30 2020 - 12:45:29)
Trying to boot from MMC1

 

calibration result:


============================================
DDR Stress Test (3.0.0)
Build: Dec 14 2018, 14:13:23
NXP Semiconductors.
============================================

============================================
Chip ID
CHIP ID = i.MX6 UltraLiteLite(0x65)
Internal Revision = TO1.1
============================================

============================================
Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00002260
SRC_SBMR2(0x020d801c) = 0x02000001
============================================

ARM Clock set to 528MHz

============================================
DDR configuration
DDR type is DDR3
Data width: 16, bank num: 8
Row size: 16, col size: 10
Chip select CSD0 is used
Density per chip select: 1024MB
============================================

Current Temperature: 41
============================================

DDR Freq: 396 MHz

ddr_mr1=0x00000000
Start write leveling calibration...
running Write level HW calibration
MPWLHWERR register read out for factory diagnostics:
MPWLHWERR PHY0 = 0x00000000


HW WL cal status: no suitable delay value found for byte 0

HW WL cal status: no suitable delay value found for byte 1
Write leveling calibration completed but failed, the following results were found:
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x001F001F
Write DQS delay result:
Write DQS0 delay: 31/256 CK
Write DQS1 delay: 31/256 CK


Error: failed during write leveling calibration

 

Stress test result:

============================================
DDR Stress Test (3.0.0)
Build: Dec 14 2018, 14:13:23
NXP Semiconductors.

============================================
Chip ID
CHIP ID = i.MX6 UltraLiteLite(0x65)
Internal Revision = TO1.1

============================================
Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00002260
SRC_SBMR2(0x020d801c) = 0x02000001

ARM Clock set to 528MHz

============================================
DDR configuration
DDR type is DDR3
Data width: 16, bank num: 8
Row size: 16, col size: 10
Chip select CSD0 is used
Density per chip select: 1024MB

DDR Stress Test Iteration 1
Current Temperature: 51

DDR Freq: 297 MHz
t0.1: data is addr test
Address of failure(step2): 0x80000000
Data was: 0xffffffff
But pattern should match address
Error: failed to run stress test!!!

    

 

Here is the schematic of our board. I think it is very similar to the design of imx6ullevk.     

     Capture.PNG

Thank you for your help first.

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2 Replies

109 Views
AccuJie
Contributor III

We have found the problem. It is caused by missing connection between NVCC_DRAM_2P5 and VDD_HIGH_CAP.

Thanks for your help.

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161 Views
igorpadykov
NXP TechSupport
NXP TechSupport

Hi AccuJie

 

"Error: failed during write leveling calibration" may point to hardware

issues: incorrect routing of ddr lines, broken or shortened signals.

Probably poor soldering, try to resolder chip.

May be recommended to check signals with oscilloscope, use guidelines of

Hardware Development Guide for the i.MX 6ULL Applications Processor

 

Best regards
igor