Hi,
Thank you for the answer. However I now have some more questions and observations. There are clock numbers that appear on both tables 9-1 and 9-2 (asrck_clock_4, 7, c and d).
Also in table 9-1 it says that the 4-position mux is controlled by 2 bits in the IOMUX GPR0 register (bits 16:17, 18:19, 20:21 and 22:23) but looking at that register definition the bits are marked as reserved (see image below section 32.4.1 page 1475-1476).

By comparing the documentation with the one of the IMX6D/Q I saw that in the IMX6DQRM there are no duplicate clock numbers in tables 9-13/9-14 (ASRC Muxed Input Clocks/ASRC Direct Clocks page 502/503) which seems to make more sense to me.
Also in this reference manual the IOMUX GPR0 register is indeed used to configure the asrc input clocks.
Is it an error in the IMX6ULL reference manual GPR0 description? Or is table 9-1 Mux4:1 Control column wrong?
Thank you
Manuel BA