IMX6UL OCRAM

[paulbox23]

Hi,

I have been looking at the ""documentation"" for OCRAM in the IMX6ULL ref manual.

It seems to have mysterious 'advanced features' designed to avoid timing issues..

These advanced features are controlled by IOMUXC.GPR3 and configure wait states and pipe lining. It seems that at 'higher frequency' these features are required to avoid potential timing problems.

What are these potential timing problems?? Does the read / write fail or lock up or does that chip just explode?

What exactly is 'higher frequency'? When should wait states and pipe lining be enabled?

I have checked the ref manuals for many IMX6 devices and they contain the same cut-and-paste info. 

Cheers

Paul

[Bio_TICFSL]

Hello Paul,

According to app note AN12077 (Using the i.MX RT FlexRAM) OCRAM is used during boot:

The minimum configuration of OCRAM is 128 KB I guess is for MX6UL.  This is required due to ROM code requires at least

64 KB of RAM for its execution (device dependent). 

https://www.nxp.com/docs/en/application-note/AN12077.pdf 

  Customers can use OCRAM (after boot) as needed, in particular - for buffers.

  App note AN12437 (i.MX RT Series Performance Optimization) states, that "OCRAM shows higher

performance than TCM when accessed by DMA, while lower performance when accessed by MCU core.

The reason is that OCRAM and DMA are in this same bus fabric, with less latency during the access."

https://www.nxp.com/docs/en/application-note/AN12437.pdf 

Of course, you can use a small OS-less applications running in OCRAM only not using DRAM. However, the functionality of such applications seems to be very limited due to small amount of memory available. On the other hand, it is possible to run the code directly from, for example, external parallel NOR flash using the External Memory Interface module and use OCRAM for stack/data only. The limitations here are: 1) relatively slow EIM operation and 2) relatively small address space of up to 128MBytes.

Regards

[paulbox23]

Hi, Thanks for the feedback.

But my question is about the performance bits in IOMUXC.GPR3 in IMX6UL (not RT)

These performance bits are used to insert wait states and pipelining when the OCRAM (AXI bus I assume) is accessed at a 'higher frequency'. The reference manual does not specify what 'higher frequency' is

Please take a look at i.MX 6UltraLite Applications Processor Reference Manual  Section 36.3

At what bus speed are these wait states required? 

Cheers

Paul