IMX6UL_14x14 BDSL DRAM_SDCLK0_P signal

[jamesk1]

In The IMX6UL_14x14 BDSL file the DRAM_SDCLK0_P signal is set to be bidirectional. The JTAG is unable to read the correct signal back which leads me to believe that the PAD is an output only PAD. Could you confirm this please

[Yuri]

Hello,

  Please check JTAG signals and configuration using Table 8 (JTAG recommendations),

sections 7.5 (Boundary scan operation) and 7.6 (I/O pin power considerations) of

Hardware Development Guide for the i.MX 6UltraLite Applications Processor, Rev. 1, 03/2016.

BSDL file :

https://www.nxp.com/webapp/Download?colCode=IMX6_UL_BSDL&appType=license&Parent_nodeId=1431012586080... 

Have a great day,
Yuri

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[jamesk1]

Hi

In the generic (PHYSICAL_PIN_MAP : string := "BGA") the DRAM_SDCLK0_P is defined as an "OUT"

but then in the "attribute BOUNDARY_REGISTER of MX6UL: entity is" section it is defined as "bidir"

Hence when a connection test in running on it it believes it is able to read an input from the DRAM_SDCLK0_P pin.

I have changed bidir to output3 believing this is what it should be set as?

could you please confirm this?

[Yuri]

Hello,

  You may change the original BSDL file if it does not contradict Your testing procedure.

Regards,

Yuri.