@2548903578
Hello,
We do not have examples regarding SDMA events, nevertheless
below are some comments.
Input signals SDMA_EXT_EVENT0, SDMA_EXT_EVENT1 are used as external
DMA request event signals and are designed to trigger internal DMA transactions.
The external request works as an internal request triggered by a FIFO.
It is needed to provide (in software) :
- source address of the FIFO (external memory address) ;
- destination address in RAM or wherever ;
- count (total number of bytes to exchange) ;
- burst length (close to the watermark level of the FIFO that triggers the DMA event).
Then, a DMA event triggers a DMA channel. Depending on the channel priority
an access is done to an external device FIFO through the EIM, assuming the external
device is connected via the EIM and can assert request (via SDMA_EXT_EVENTx).
Practically the access looks like as usual CPU-related one, at least the
external device cannot distinguish between DMA and CPU ones, because both are
working via the EIM, and fully defined by EIM settings.
The selected burst length defines length (duration) of this access.
If the DMA event signal is still asserted, the access will continue with a next
burst, if not - the DMA waits for a next event to do an access.
Indeed, there is no real flow control, but the external peripheral should be
enable to generate some DMA event each time its FIFO has reached a watermark level.
Note, there is no need for external grant / acknowledge signal.
Taking into account considerations above - it is not clear what is source
of the SDMA_EXT_EVENTx and how it is controlled in case of memory-to-memory
transfer.
Regards,
Yuri.
