IMX6SX IPG clock conflict, IMX_CONSOLE and FEC with RMII PHY at 50MHz

[samkreuze]

I have a custom imx6sx board which had been running yocto fido with a LAN8710 phy. I have patches for fido which allow the NXP FEC driver to interface with the PHY. These include setting the clock to 50MHz and setting the pins appropriately. These changes are nearly identical to what BiyongSUN suggests here: https://community.nxp.com/t5/i-MX-Processors/RMII-interface-on-i-MX6SX/m-p/424530

I am now updating this board to yocto zeus. I cannot get the ethernet to function without disabling the IMX_CONSOLE.  I believe changes to the FEC and IMX serial console drivers have created conflicts with each other when manipulating the IPG clock. 

I am trying to develop a patch that allows for both devices to function simultaneously but am having difficulty. Does anyone have such a patch already? 

[stew · Accepted solution]

@samkreuze's colleague here. After some investigation, we found a workaround. Here's the patch:

From: Stewart Hildebrand <stewart.hildebrand@dornerworks.com>
Date: Mon, 2 Aug 2021 10:56:07 -0400
Subject: [PATCH] imx_uart: disable DTRD interrupt

We are seeing an issue where enabling an Ethernet clock breaks the UART and
hangs the system. The system hangs due to the UART interrupt Data Terminal
Ready Delta (DTRD) interrupt continuously triggering.

The DTRD interrupt was enabled in the following commit, included in our Zeus
build based on Linux rel_imx_5.4.70_2.3.0:

  27e16501052e serial: imx: implement DSR irq handling for DTE mode

We were using Linux rel_imx_3.14.52_1.1.0_ga in the old Fido build, which did
not have that commit, and this explains why we didn't see the issue before.

The issue presents itself while the code is in a very specific place inside of
the Ethernet driver (fec_enet_open), specifically after enabling an Ethernet
reference clock and re-enabling interrupts. We observed this after changing the
Ethernet reference clock from 125MHz to 50MHz, but we are unsure if the problem
would also present itself when the clock is at its default 125MHz (our PHY
requires a 50MHz reference clock).

The "data set ready" pin (DSR_B) is an input since we're operating the uart in
DTE mode. According to the i.MX6SX TRM, a change to the DSR_B pin will generate
an interrupt, and in our case we were seeing that interrupt being triggered
continuously. This interrupt is for modem status signal handling, and is not
required for our use case. The DSR_B signal isn't present on the other UARTs.
DSR_B is an optional modem status signal that isn't connected in the schematic.

As a workaround for the issue, this patch disables the DTRD interrupt, and both
Ethernet and console are working now.

Signed-off-by: Stewart Hildebrand <stewart.hildebrand@dornerworks.com>
---
 drivers/tty/serial/imx.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 43c6d7142fdd..a9a4a6922c73 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -1440,12 +1440,15 @@ static int imx_uart_startup(struct uart_port *port)
 
 		ucr3 = imx_uart_readl(sport, UCR3);
 
-		ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
+		ucr3 |= UCR3_RI | UCR3_DCD;
 
 		if (sport->dte_mode)
 			/* disable broken interrupts */
 			ucr3 &= ~(UCR3_RI | UCR3_DCD);
 
+		/* disable another broken interrupt */
+		ucr3 &= ~(UCR3_DTRDEN);
+
 		imx_uart_writel(sport, ucr3, UCR3);
 	}
 
-- 
2.32.0

[b36401]

We have no such patch.
Sorry for the inconvenience.