IMX6SDL IPUx_CSIx_VSYNC,HSYNC; active-high/low and rising/falling-edge triggered IPU_CSI_PIX_CLK.

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IMX6SDL IPUx_CSIx_VSYNC,HSYNC; active-high/low and rising/falling-edge triggered IPU_CSI_PIX_CLK.

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Contributor III

Dear community.

Our customer has question below.

IMX6SDLAEC P94 of 4.11.10.2.3 Non-Gated Clock Mode  describe that rising / falling edge and active HI / Lo can be changed,
Where should I refer to specific settings?

The timing described in Figure 61 is that of a typical sensor. Some other sensors may have a slightly
different timing. The CSI can be programmed to support rising/falling-edge triggered
IPUx_CSIx_VSYNC; active-high/low IPUx_CSIx_HSYNC; and rising/falling-edge triggered
IPUx_CSIx_PIX_CLK.

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NXP TechSupport
NXP TechSupport

Hi Takashi

please refer to sect.38.5.151 CSI0 Sensor Configuration Register i.MX6SDL Reference Manual

(IPUx_CSI0_SENS_CONF) for description of polarity bits 0-3.

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6SDLRM.pdf 

Best regards
igor
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NXP TechSupport
NXP TechSupport

Hi Takashi

please refer to sect.38.5.151 CSI0 Sensor Configuration Register i.MX6SDL Reference Manual

(IPUx_CSI0_SENS_CONF) for description of polarity bits 0-3.

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6SDLRM.pdf 

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

View solution in original post

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