IMX6S Micrel KSZ8794 RGMII no network connectivity

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IMX6S Micrel KSZ8794 RGMII no network connectivity

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aduskett
Contributor II

Hi! My company is spinning it's own board with a MCIMX6S6AVM08AC as it's main processor.  Currently we are in the board bring-up stage, and I am running into some serious problems getting any network traffic out of the Micrel chip, so I was hoping to get a confirmation on our setup.

Here is a link to the KSZ8794 datasheet for reference: http://ww1.microchip.com/downloads/en/DeviceDoc/00002134A.pdf 

Below is our layout, as you can see, GPIO_16 is not connected and ENET_REF_CLK is connected to a external 125Mhz oscillator running at 1.8 volts.

ethernetKSZ8794CNX.jpg

As per the IMX6DQ6SDL hardware development guide pdf, page 12-7, figure 12.5, I am clearing GPR1[21] in the uboot file.  

Here is my current configuration for the Micrel in uboot:

#define ETH_PHY_RESET IMX_GPIO_NR(1, 25)

static const iomux_v3_cfg_t enet_pads[] = {
    NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL),
    NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC , ENET_PAD_CTRL),
    NEW_PAD_CTRL(MX6_PAD_RGMII_TXC__RGMII_TXC, ENET_PAD_CTRL),
    NEW_PAD_CTRL(MX6_PAD_RGMII_TD0__RGMII_TD0, ENET_PAD_CTRL),
    NEW_PAD_CTRL(MX6_PAD_RGMII_TD1__RGMII_TD1, ENET_PAD_CTRL),
    NEW_PAD_CTRL(MX6_PAD_RGMII_TD2__RGMII_TD2, ENET_PAD_CTRL),
    NEW_PAD_CTRL(MX6_PAD_RGMII_TD3__RGMII_TD3, ENET_PAD_CTRL),
    NEW_PAD_CTRL(MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL, ENET_PAD_CTRL),
    NEW_PAD_CTRL(MX6_PAD_ENET_REF_CLK__ENET_TX_CLK, ENET_PAD_CTRL),
    NEW_PAD_CTRL(MX6_PAD_RGMII_RXC__RGMII_RXC, ENET_PAD_CTRL),
    NEW_PAD_CTRL(MX6_PAD_RGMII_RD0__RGMII_RD0, ENET_PAD_CTRL),
    NEW_PAD_CTRL(MX6_PAD_RGMII_RD1__RGMII_RD1, ENET_PAD_CTRL),
    NEW_PAD_CTRL(MX6_PAD_RGMII_RD2__RGMII_RD2, ENET_PAD_CTRL),
    NEW_PAD_CTRL(MX6_PAD_RGMII_RD3__RGMII_RD3, ENET_PAD_CTRL),
    NEW_PAD_CTRL(MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL, ENET_PAD_CTRL),
};

static void setup_iomux_enet(void){
    imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));

    gpio_direction_output(ETH_PHY_RESET, 0);
    udelay(1000 * 10);
    gpio_set_value(ETH_PHY_RESET, 1);
    mdelay(100);
}


static int setup_fec(void){

    /* Turn off GPR1[21] as per page 12-7, figure 12.5 of the IMX6DQ6SDL */

    imx_iomux_set_gpr_register(1, 21, 1, 0);
    setup_iomux_enet();
    return 0;
}


int board_eth_init(bd_t *bis){
    setup_fec();
    return cpu_eth_init(bis);
}

In the drivers/net/phy/micrel.c file I have added the following:

int ksz8794_config(struct phy_device *phydev){
    /* we are connected directly to the switch without dedicated PHY. */
    phydev->link = 1;
    phydev->duplex = DUPLEX_FULL;
    phydev->speed = SPEED_1000;

    /* Default settings to register 0x0, page 137 or KSZ8794 TRM. */
    phy_write(phydev, MDIO_DEVAD_NONE, 0x0, 0x3120);

    return 0;
}


int ksz8794_startup(struct phy_device *phydev){
     unsigned phy_ctl;
     int ret;
     ret = genphy_update_link(phydev);
    if (ret){
        return ret;
    }
    return 0;

}


static struct phy_driver KSZ8794_driver = {
    .name = "Micrel KSZ8794 Switch",
    .uid = 0x221550,
    .mask = 0xfffff0,
    .features = PHY_GBIT_FEATURES,
    .startup = &ksz8794_startup,
    .shutdown = &genphy_shutdown,
    .config = &ksz8794_config,
};

int phy_micrel_init(void) {
    phy_register(&KSZ8794_driver);

    phy_register(&KSZ8794_driver);
    phy_register(&KSZ804_driver);
    phy_register(&KSZ8031_driver);
    phy_register(&KSZ8051_driver);
    phy_register(&KSZ8081_driver);
    #ifdef CONFIG_PHY_MICREL_KSZ9021
        phy_register(&ksz9021_driver);
    #else
        phy_register(&KS8721_driver);
    #endif
    phy_register(&ksz9031_driver);
    phy_register(&ksz8895_driver);
    phy_register(&ksz886x_driver);
    return 0;
}

When I boot uboot everything looks good!

eth_init: fec_probe(bd, -1, 1) @ 02188000
fec_mii_setspeed: mii_speed 0000001a
fec_mdio_read: Phy Address: 0x1 Register:0x2 Value:0x22
fec_mdio_read: Phy Address: 0x1 Register:0x3 Value:0x1550
fec_mii_setspeed: mii_speed 0000001a
fec_mdio_write: Phy Address: 0x1 Register:0x0 Value:0x8000
fec_mdio_read: Phy Address: 0x1 Register:0x0 Value:0x0
FEC connected to Micrel KSZ8794 Switch

However; when I attempt to run dhcp I am unable to get a address:

~]$ dhcp
eth_halt: wait for stop regs
eth_halt: done
Trying FEC
fec_mii_setspeed: mii_speed 0000001a
fec_open: fec_open(dev)

fec_mdio_read: Phy Address: 0x1 Register:0x1 Value:0x782c
fec_open:Speed=1000
BOOTP broadcast 1
fec_send: status 0xc00 index 0 ret 0
fec_recv: ievent 0xc000000
fec_recv: status 0x8000
fec_recv: stop

(This repeats in a loop for several hundred lines until all 17 tries are finished.)

Now, at this point, I am pretty much out of ideas.  I originally thought that perhap TskewT needed to be modified, however after scoping RGMII_TXC and RGMII_TD0 the data and clock seem to line up almost perfectly, well within spec I believe.

20160922_153322.jpg

I have connected our board to a dumb hub along with my PC and wireshark shows absolutely nothing when running DHCP from the uboot. 

At this point I have confirmed that both RXC and TXC output a 125Mhz clock, and I can talk to the Micrel, however I am still not able to get network traffic.  At this point I need the help of the community to assertain what on earth is going on, and ANY help would be GREATLY appreciated!

Does my uboot config look correct?

Does the Schematic look correct?

Do the scope measurements look correct?

Thank you so much!

Adam

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aduskett
Contributor II

Hey Artur;

Thanks for the suggestion!  As you can see on both the scope screenshot, and the schematic, we have a 125MHz oscillator already working and functioning properly with the ENET_REF_CLK.

We did however solve the problem if anybody is curious:

The problem was that the drive strength was too strong on TXC.  Changing the DSE from 34ohm to 240ohm on MX6_PAD_RGMII_TXC__RGMII_TXC fixed the issue completely. 

View solution in original post

4 Replies
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emreertaş
Contributor I

Hi Adam,

According to your schematic your MDC-MDIO connection between cpu and ethernet switch is crossed. Is it correct connection or not?

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emreertaş
Contributor I

scl/mdc was labelled as enet_mdio while sda/mdio was labelled enet_mdc. They are wrong labels I guess.

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art
NXP TechSupport
NXP TechSupport

The most likely cause of the issue is that the Ethernet PHY and the RGMII port of the i.MX6 processor don't have the common reference clock, as it should be. The 125MHz RGMII reference clock should be either generated by an external reference clock source and provided to both the clock input of the PHY and the ENET_REF_CLK input of the processor, or generated by PHY and then connected to the ENET_REF_CLK input of the processor. So, you have to modify your schematic according to this requirement. Please use the schematic of the i.MX6 SABRE SD board as the reference.


Have a great day,
Artur

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aduskett
Contributor II

Hey Artur;

Thanks for the suggestion!  As you can see on both the scope screenshot, and the schematic, we have a 125MHz oscillator already working and functioning properly with the ENET_REF_CLK.

We did however solve the problem if anybody is curious:

The problem was that the drive strength was too strong on TXC.  Changing the DSE from 34ohm to 240ohm on MX6_PAD_RGMII_TXC__RGMII_TXC fixed the issue completely. 

View solution in original post