IMX6Q the clk of DDR3 when using fly-by topology (Very Urgent)

[weivivien]

hello,

We have a very urgent problem about iMX6Q and DDR3.

According to the design of IMX6Q reference design, it use four DDR chips with T-topology and use two pair of CLK(CLK0 CLK0# and CLK1 CLK1#) and one cs signal.

In our design, we have a special cross section of PCB, so we can't use T-topology, so we decide to use fly-by topology.

BUT, we have question ahout CLK and CS.

Could we still use 2 pair of clk and  ONE CS signal to monitor 4 chips of DDR3(just like the schematic of reference design in T-topology and add termination res).or we have to use 1 pair of clk and 1CS signal to control 4 DDR chips

thank you very much!

vivien

[igorpadykov]

Hi vivien

in that case recommended  to use 1 pair of clk and 1CS signal to control 4 DDR chips

Best regards
igor
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[weivivien]

Thank you very much for your reply!

But our BSP bootloader of DDR is writed for 2 pair of clk signals to control 4 DDR chips, can we still use 2 pair of CLK in fly-by topology?

Because it's an challenge for us to edit the BSP bootloader. 

Best regards
vivien

[weivivien]

Thank you very much for your reply!

But now we can't understand why their is two CLK for 4 DDR chips in T-topology and just one CS signal.