IMX6Q DDR3 can‘t work

[jhduan]

Hi，I have a custom board with IMX6Q and DDR3(2GB).

Using the tool of DDR Stress tester,432MHz pass,but 452MHz fail.

I download the special uboot and image using manufacturing tool (imx_usb), but I don't see any serial port messages. Last week, there are some messages print out, but now it doesn't work.

I check the follows:

1/ the clocks (24MHz and 32.768KHz) are fine;

2/ the power-up sequence meets the arm's requirement;

3/ the voltages for arm and DDR3 are fine. but there is some ripple on DDR3 power(between +-30mV).

4/ using the fly-by topology. terminating resistors have changed from 22ohm to 47ohm, but no effect.

Now, what should I do?

Any pointers?

[Selea]

the ddr3 routing is often very critical... did you used the routing suggested in on on the freescale ref des?

the problems could be:

routing, power supply, lines capacitance, and difference between lines path.

Check the pcb issue first.

Omar

[jhduan]

I add some decoupling capacitors near the terminating resistors. Now, Using the tool of DDR Stress tester,528MHz pass.

But a new trouble comes. when I download the uboot and image to my board using MFGtools . the tool stop at "jumping to OS image", while no messages print out from  the serial port. I try several times, but get the same result.

why special uboot can't run from DDR3,while the DDR TEST is ok.

Looking forward to your reply.

[Selea]

not easy to give you an answer, it seems to be an hardware issue....

the different behaviour with different tests, or with just a capacitor, means some pcb problem.

it's very critical, this is the reason the we often use the suggested routing by the freescale (taking it directly from a evaboard.)

can you try also with a different DDR manufacturer... could be another test....

[jhduan]

I got it. the solution is adding enough decoupling capacitors on Vtt.

[anujsinghvi]

Hi,

I am also getting same issues that DDR3.  Issue is:

1.  DDR3 write leveling calibration getting failed on 528MHz but Stress Test getting passed till 596MHz.

2.  In my design, out of 4 DDR3 chip 2 has swapped LDM and UDM (middle 2 from D16-D47).

3.  DDR3 write leveling calibration is passed at 400MHz even with swapped LDM and UDM?

I am not sure whether swapped LDM/UDM, LDQS and UDQS will really cause issue on higher frequencies but not on lower frequencies.  I am using Fly By topology.

I am not able to get boot from DDR3 in any case whether low frequency (400MHz) or Higher Frequency (528MHz).

Please let me know if you have seen the same issues in your design.

[Selea]

Great!...

please mark this as solved.