Hello!
A am engineer from Ukraine.
A have a task: created board with IMX6 Dual Lite, 4 Gbyte DDR3.
In "Document Number: IMX6SDLRM Rev. 2, 04/2015" page 3911 write:
"If the DDR memory space allocation is 4 Gbytes, only one configuration of chip select
partition is allowed.
The register MDASP[CS0_END] should be set to 011_1111 (partition at 2 Gbytes).
The figure below shows the associated memory space. In the case of DDR3 x64, this
address space can be acheived by connecting four devices per chip select. Each device is
x16 with density of 4 Gbytes."
"Each device is x16 with density of 4 Gbytes" or Each device is x16 with density of 4 Gbits ?
If I get you right, i can not create 4 Gbyte space from 4 chip of each chip 8Gbit ?
Hello,
sure, the Dual Lite is supporting an adressable range of 4GB, and you can reach it in two ways:
a) using 4 devices DDR3L 8Gbit x16 monolithic from either Micron (MT41K512M16...) or from Intelligent memory (IM8G16D3F...)
b) using 2 devices LPDDR2 16Gbit x32 with two CS like Micron/Elpida
depending on the Flash device you are using (raw NAND or eMMC) there could be also a eMCP or normal MCP an additional solution. Hope, that helps you.
have a nice weekend, Lars
Hello Lars,
We are using 4 devices DDR3L MT41K512M16HA; It is possible to address all 4GB of DDR3L memory using only one CS(We are only using CS0). Is this right?
Thank you very much!
Kyle
Yes. It is misprint. Here should be noted 8Gbit.
Have a great day,
Victor
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Hello Lars,
We are using 4 devices DDR3L MT41K512M16HA; It is possible to address all 4GB of DDR3L memory using only one CS(We are only using CS0). Is this right?
Thank you very much!
Kyle