IMX6D ARM_CLK_ROOT and PLL1

[tomsaluzzo]

I am confused by the relationship of the ARM Core Clock and PLL1.

Referring to the IMX6DQRM Rev 3

The diagrams in Figure 18-2 (page 796) and Figure 18-6 (page 818) shows a fixed divide by 2 block from PLL1 for the ARM_CLK_ROOT.

The equation from page 901 is: PLL Output Frequency = Fref * DIV_SEL / 2.

Is the divide by 2 in the equation from page 901 CCM_ANALOG_PLL_ARMn:DIV_SELECT the divide by 2 block in Figure 18-6?

(i.e. the equation on page 901 should be: ARM_CLK_ROOT = Fref * DIV_SEL / 2).

Otherwise, you couldn’t have an ARM_CLK_ROOT frequency of 996MHz because the DIV_SEL value would have to be 166 decimal, which is above the valid range of values (54-108).

[igorpadykov]

HI Tom

you are right, equation should be:

ARM_CLK_ROOT = Fref * DIV_SEL / 2

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

[tomsaluzzo]

You did not answer the question I asked. I was not questioning the equation.

I asked:

Is the divide by 2 in the equation from page 901 CCM_ANALOG_PLL_ARMn:DIV_SELECT the divide by 2 block in Figure 18-6?

In other words, in Figure 18-6, is the divide by 2 block represented in the ARM_CLK_ROOT equation or is it not included in the equation?

[igorpadykov]

>Is the divide by 2 in the equation from page 901 CCM_ANALOG_PLL_ARMn:DIV_SELECT the divide by 2 block in Figure 18-6?

yes.