IMX6 audio clock

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IMX6 audio clock

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will_intelli
Contributor III

Hi,

I have an imx6qp-based custom board which uses an sgtl5000 codec.  I'm using a build of Linux based on the 4.14.62-imx_4.14.62_1.0.0_beta branch of linux-imx.  The master clock on the sgtl5000 is sourced from the I2S clock output, so I need this clock to be active before I go to load the driver module for the sgtl5000.   Is there a way to configure the dts to force the clock on?  I have this at the moment:

    sound-sgtl5000 {
        compatible = "fsl,imx-audio-sgtl5000";
        model = "imx-sgtl5000";
        esai-controller = <&esai>;
        asrc-controller = <&asrc>;
        ssi-controller = <&ssi2>;
        audio-codec = <&codec>;
        audio-routing =
            "MIC_IN", "Mic Jack",
            "Mic Jack", "Mic Bias",
            "Headphone Jack", "HP_OUT";
        mux-int-port = <1>;
        mux-ext-port = <4>;
    };

&ssi2 {
    assigned-clocks = <&clks IMX6QDL_CLK_SSI2_SEL>;
    assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
    assigned-clock-rates = <0>;
    fsl,mode = "i2s-master";
    status = "okay";
};

Thanks,

Will.

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igorpadykov
NXP Employee
NXP Employee

Hi Will

sgtl5000 is supported in boundary devices imx6qp nitrogen board and one can look at its dts :

linux-imx/imx6qp-nitrogen6_som2.dts at imx_4.14.78_1.0.0_ga_var01 · varigit/linux-imx · GitHub 
linux-imx/imx6qdl-nitrogen6_som2.dtsi at imx_4.14.78_1.0.0_ga_var01 · varigit/linux-imx · GitHub 

Best regards
igor
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will_intelli
Contributor III

Hi,

It looks like that board has the sgtl5000 master clock connected to the CCM_CLKO1 output and is enabling that clock in the codec dts configuration. 

On my board I have the master clock connected to the I2S transmit clock, specifically DISP0_DAT16 - AUD5_TXC.  Normally this clock output would only be active after the interface is enabled, is it possible to enable this output beforehand (eg. on boot) so the codec can get picked up by an I2C scan?

Will.

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igorpadykov
NXP Employee
NXP Employee

one can check master clock generation, as according to sect.61.1.1 Features i.MX6DQ Reference Manual :

"..oversampling clock to external device available as output from SRCK in I2S Master mode..

SSI's system clock (generated inside CCM) can be used in I2S Transmitter Master
mode. This system clock is also available as source clock for output SRCK in master
mode, when operated in sync mode."

http://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf

Best regards
igor

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