IMX6 SSI clock for I2S Mode

cancel
Showing results for 
Search instead for 
Did you mean: 

IMX6 SSI clock for I2S Mode

Jump to solution
2,152 Views
sriramperiyasam
Contributor II

Hi All,

I am using the SSI1 as I2S master and configured the registers as per the Reference manual for SABRESD AndroidKK4.4.2.

for 2 channel, 48KHz, 16 bit depth audio data,

  SSI1 clock -> 12.288 MHz derived from Audio PLL4 ( 688.128 )

 

enabled the network clock as follows,

snd_soc_dai_set_sysclk(cpu_dai, IMX_SSP_SYS_CLK, 0 , SND_SOC_CLOCK_OUT);

And the dividers are as follows

WL - 7 ( 16 bit )

DC - 1 ( 1 frame )

PM - 3

DIV2 - 0

PSR - 0

And dumped the register for above values. Still i am not getting proper Bit clock 1.5 Mhz in clock line.

I am getting ~6 MHz in clock line.

Can anyone please help me that what i am missing in the configuration.

Your help will be grateful.

Thanks and Regards,

Sriram.

Labels (6)
0 Kudos
1 Solution
149 Views
saurabh206
Senior Contributor III

Hi

Sriram

Your understanding is correct regarding in master mode I2S mode always generates 32 bits per word.

You should configure your codec about i2s setting.

Thanks

Saurabh

View solution in original post

0 Kudos
5 Replies
149 Views
sriramperiyasam
Contributor II

Hi,

And also there is no sample clock dividers mentioned in the Reference manual for I2S mode.

Did anyone used IMX as I2S master for different frequencies and sample rates?. Please share your views.

It is bit fuzzy for I2S Mode in IMX6.

Regards,

Sriram.

0 Kudos
149 Views
saurabh206
Senior Contributor III

Hi

Sriram

You can study

kernel_imx\sound\soc\imx\imx-si4763.c  imx_3stack_si4763_hw_params(),

Following code is used to set the divider. You need to configure those value according to your requirement.

    snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_PM, 1);

    snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_2, 1);

    snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_PSR, 0);

Thanks

Saurabh

0 Kudos
149 Views
sriramperiyasam
Contributor II

Hi Saurabh,

Thanks for your reply. I tried your suggestion already as follows,

snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_PM, 3);

snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_2, 0);

snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_PSR, 0);

with the configurations

for 2 channel, 48KHz, 16 bit depth audio data,

SSI1 clock -> 12.288 MHz derived from Audio PLL4 ( 688.128 )

But still the result is same. And i have few queries about the I2S mode in SSI

1. I came to know that I2S mode always generates 32 bits per word, so should i change the SSI sys clock

2. if so, the bit clock freq will be 32 * 2 * 48000 = 3072000 Hz. Then how to calculate frame sync freq for 48 KHz. Whether is it correct as per I2S protocol

3. If 32 bits per word used, whether external Audio codec should have the intelligence to filter out the valid 16 bits out 32 bits transmitted from IMX and to send 16 bits valid data with 16 bits stuffed to IMX.

Thanks for your valuable time.

Regards,

Sriram.

0 Kudos
150 Views
saurabh206
Senior Contributor III

Hi

Sriram

Your understanding is correct regarding in master mode I2S mode always generates 32 bits per word.

You should configure your codec about i2s setting.

Thanks

Saurabh

View solution in original post

0 Kudos
149 Views
sriramperiyasam
Contributor II

Thanks Saurabh. I will try to configure my codec.

0 Kudos