IMX6 Quad and Dual boot issue from eMMC

[yongwoolee]

@Hi. I am developing the board with IMX6 Quad and Dual.

Both have the boot issue when it powers on. Only when the power is on within 3 seconds or less, the board is booting from the eMMC properly. Otherwise, the board always goes into USB serial boot mode.

When the POR_B is reset again, then it boots normally.

This board is using

- MCIMX6Q5EYM10AD

- PF0100NPEAP which is using the same script of F0 pre-programmed

- 4 DDR3

- 4G eMMC

Actually, I have done the same project with IMX6-Dual and 2 DDR3. This board is working perfectly.

Basically, both projects with 2 DDR3 and with 4 DDR3 are identical. Same Dual processor and same PMIC PF0100NPEAP.

However, the board with 4 DDR3 has the boot issue as I described above.

According to the errata, I add the 1uF on the POR_B to make a delay until the 32KHz external crystal gets stable and other power rails.

I can search the similar issue related to the boot. Do you have any solution about it?

[yongwoolee]

Hi Igor

As I mentioned, the board is using the F0 Script which is used on the Sabre reference board.

The power sequence is exactly identical to F0's. Then, how could the power sequence cause the issue?

Can you explain it in detail?

Best regards,

[igorpadykov]

Hi Yongwoo

please check Chapter 4 Requirements for Power Management

i.MX6 System Development User’s Guide

http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf

and sect.4.2.1 Power-Up Sequence i.MX6DQ Datasheet

http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6DQCEC.pdf

suggest to look at below links solutions with similar problem

https://community.freescale.com/thread/338433

IMX6SOLO initial power up boot up issue

Best regards

igor

[yongwoolee]

Hi Igor

Yes, it does.

According to our test, it seems that eMMC loads correctly and all the DCDs
register settings are applied properly, the problem starts later on when the
ROM code moves on to initializing the DDRs - if that matters.

- I run the DDR stress test with 400MHz and 566MHz. Both clock frequency succeed with no issue.

- One symptom is that

Before loading the boot image on eMMC, our board goes into the serial boot mode. However, it doesn't start the u-boot properly from the serial boot mode with mfg-tool. It is always stuck until the POR_B is reset again.

- Another symptom is that

If the VDD_HIGH_IN is tied directly with VSNVS via coin-cell battery which is charged up to 1V, the board is always booting properly.

[igorpadykov]

Hi Yongwoo

>If the VDD_HIGH_IN is tied directly with VSNVS via coin-cell battery which is

>charged up to 1V, the board is always booting properly.

this points that issue is related to power-up sequence

Best regards

igor

[yongwoolee]

Hi Igor

This is the info of SRC_SBMR1/2 from Jtag.

md 0x020d8004 1

   020d8004 : 0x00002060         8288  ` ..

md 0x020d801c 1

   020d801c : 0x28000011    671088657  ...

Best regards,

[igorpadykov]

Hi Yongwoo

do they correspond values set by boot pins ?

Best regards

igor

[yongwoolee]

Hi Igor

One more symptom when I tested the DDR.

When the board doesn't turn on/off/on quickly within 3 seconds, the board is stuck although it goes into the serial boot mode automatically.

At the serial boot mode for DDR test, the freescale DDR Test tool shows the error like below when I tried to load the "init Script".

"ERROR: Write dcd failed."

By the way, I also tested the internal oscillator instead of the external 32.768KHz followed by the errata. But, it doesn't help fix the boot issue.

In addition, I extend the POR_B manually up to around 1 seconds and release it to run the IMX. This doesn't help either.

This is the result of the calibration when the board goes into the serial boot mode normally.

============================================

        Chip ID

CHIP ID = i.MX6 Dual/Quad (0x63)

Internal Revision = TO1.5

============================================

============================================

        Boot Configuration

SRC_SBMR1(0x020d8004) = 0x00002060

SRC_SBMR2(0x020d801c) = 0x21000011

============================================

ARM Clock set to 1GHz

============================================

        DDR configuration

BOOT_CFG3[5-4]: 0x00, Single DDR channel.

DDR type is DDR3

Data width: 64, bank num: 8

Row size: 14, col size: 10

Chip select CSD0 is used

Density per chip select: 1024MB

============================================

Current Temperature: 62

============================================

DDR Freq: 528 MHz

ddr_mr1=0x00000001

Start write leveling calibration...

running Write level HW calibration

Write leveling calibration completed, update the following registers in your initialization script

    MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00080013

    MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x002B001E

    MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x000D0025

    MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x00000000

Write DQS delay result:

   Write DQS0 delay: 19/256 CK

   Write DQS1 delay: 8/256 CK

   Write DQS2 delay: 30/256 CK

   Write DQS3 delay: 43/256 CK

   Write DQS4 delay: 37/256 CK

   Write DQS5 delay: 13/256 CK

   Write DQS6 delay: 0/256 CK

   Write DQS7 delay: 0/256 CK

Starting DQS gating calibration

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BYTE 0:

Start:   HC=0x02 ABS=0x18

End:   HC=0x05 ABS=0x4C

Mean:   HC=0x03 ABS=0x71

End-0.5*tCK:  HC=0x04 ABS=0x4C

Final:   HC=0x04 ABS=0x4C

BYTE 1:

Start:   HC=0x02 ABS=0x10

End:   HC=0x05 ABS=0x3C

Mean:   HC=0x03 ABS=0x65

End-0.5*tCK:  HC=0x04 ABS=0x3C

Final:   HC=0x04 ABS=0x3C

BYTE 2:

Start:   HC=0x03 ABS=0x10

End:   HC=0x05 ABS=0x48

Mean:   HC=0x04 ABS=0x2C

End-0.5*tCK:  HC=0x04 ABS=0x48

Final:   HC=0x04 ABS=0x48

BYTE 3:

Start:   HC=0x03 ABS=0x0C

End:   HC=0x05 ABS=0x4C

Mean:   HC=0x04 ABS=0x2C

End-0.5*tCK:  HC=0x04 ABS=0x4C

Final:   HC=0x04 ABS=0x4C

BYTE 4:

Start:   HC=0x03 ABS=0x00

End:   HC=0x05 ABS=0x48

Mean:   HC=0x04 ABS=0x24

End-0.5*tCK:  HC=0x04 ABS=0x48

Final:   HC=0x04 ABS=0x48

BYTE 5:

Start:   HC=0x02 ABS=0x10

End:   HC=0x05 ABS=0x3C

Mean:   HC=0x03 ABS=0x65

End-0.5*tCK:  HC=0x04 ABS=0x3C

Final:   HC=0x04 ABS=0x3C

BYTE 6:

Start:   HC=0x02 ABS=0x64

End:   HC=0x05 ABS=0x0C

Mean:   HC=0x03 ABS=0x77

End-0.5*tCK:  HC=0x04 ABS=0x0C

Final:   HC=0x04 ABS=0x0C

BYTE 7:

Start:   HC=0x03 ABS=0x00

End:   HC=0x05 ABS=0x34

Mean:   HC=0x04 ABS=0x1A

End-0.5*tCK:  HC=0x04 ABS=0x34

Final:   HC=0x04 ABS=0x34

DQS calibration MMDC0 MPDGCTRL0 = 0x443C044C, MPDGCTRL1 = 0x044C0448

DQS calibration MMDC1 MPDGCTRL0 = 0x443C0448, MPDGCTRL1 = 0x0434040C

Note: Array result[] holds the DRAM test result of each byte. 

      0: test pass.  1: test fail 

      4 bits respresent the result of 1 byte.   

      result 00000001:byte 0 fail.

      result 00000011:byte 0, 1 fail.

Starting Read calibration...

ABS_OFFSET=0x00000000 result[00]=0x11111111

ABS_OFFSET=0x04040404 result[01]=0x11111111

ABS_OFFSET=0x08080808 result[02]=0x11111111

ABS_OFFSET=0x0C0C0C0C result[03]=0x11011111

ABS_OFFSET=0x10101010 result[04]=0x00011011

ABS_OFFSET=0x14141414 result[05]=0x00010011

ABS_OFFSET=0x18181818 result[06]=0x00010001

ABS_OFFSET=0x1C1C1C1C result[07]=0x00010000

ABS_OFFSET=0x20202020 result[08]=0x00000000

ABS_OFFSET=0x24242424 result[09]=0x00000000

ABS_OFFSET=0x28282828 result[0A]=0x00000000

ABS_OFFSET=0x2C2C2C2C result[0B]=0x00000000

ABS_OFFSET=0x30303030 result[0C]=0x00000000

ABS_OFFSET=0x34343434 result[0D]=0x00000000

ABS_OFFSET=0x38383838 result[0E]=0x00000000

ABS_OFFSET=0x3C3C3C3C result[0F]=0x00000000

ABS_OFFSET=0x40404040 result[10]=0x00000000

ABS_OFFSET=0x44444444 result[11]=0x00000000

ABS_OFFSET=0x48484848 result[12]=0x00000000

ABS_OFFSET=0x4C4C4C4C result[13]=0x00000100

ABS_OFFSET=0x50505050 result[14]=0x01100100

ABS_OFFSET=0x54545454 result[15]=0x11101110

ABS_OFFSET=0x58585858 result[16]=0x11101110

ABS_OFFSET=0x5C5C5C5C result[17]=0x11111111

ABS_OFFSET=0x60606060 result[18]=0x11111111

ABS_OFFSET=0x64646464 result[19]=0x11111111

ABS_OFFSET=0x68686868 result[1A]=0x11111111

ABS_OFFSET=0x6C6C6C6C result[1B]=0x11111111

ABS_OFFSET=0x70707070 result[1C]=0x11111111

ABS_OFFSET=0x74747474 result[1D]=0x11111111

ABS_OFFSET=0x78787878 result[1E]=0x11111111

ABS_OFFSET=0x7C7C7C7C result[1F]=0x11111111

Byte 0: (0x1c - 0x58), middle value:0x3a

Byte 1: (0x18 - 0x50), middle value:0x34

Byte 2: (0x10 - 0x48), middle value:0x2c

Byte 3: (0x14 - 0x50), middle value:0x32

Byte 4: (0x20 - 0x58), middle value:0x3c

Byte 5: (0x0c - 0x4c), middle value:0x2c

Byte 6: (0x10 - 0x4c), middle value:0x2e

Byte 7: (0x10 - 0x50), middle value:0x30

MMDC0 MPRDDLCTL = 0x322C343A, MMDC1 MPRDDLCTL = 0x302E2C3C

Starting Write calibration...

ABS_OFFSET=0x00000000 result[00]=0x11111111

ABS_OFFSET=0x04040404 result[01]=0x10111111

ABS_OFFSET=0x08080808 result[02]=0x10110110

ABS_OFFSET=0x0C0C0C0C result[03]=0x10100010

ABS_OFFSET=0x10101010 result[04]=0x00100000

ABS_OFFSET=0x14141414 result[05]=0x00000000

ABS_OFFSET=0x18181818 result[06]=0x00000000

ABS_OFFSET=0x1C1C1C1C result[07]=0x00000000

ABS_OFFSET=0x20202020 result[08]=0x00000000

ABS_OFFSET=0x24242424 result[09]=0x00000000

ABS_OFFSET=0x28282828 result[0A]=0x00000000

ABS_OFFSET=0x2C2C2C2C result[0B]=0x00000000

ABS_OFFSET=0x30303030 result[0C]=0x00000000

ABS_OFFSET=0x34343434 result[0D]=0x00000000

ABS_OFFSET=0x38383838 result[0E]=0x00000000

ABS_OFFSET=0x3C3C3C3C result[0F]=0x00000000

ABS_OFFSET=0x40404040 result[10]=0x00000000

ABS_OFFSET=0x44444444 result[11]=0x00000000

ABS_OFFSET=0x48484848 result[12]=0x01000000

ABS_OFFSET=0x4C4C4C4C result[13]=0x01000000

ABS_OFFSET=0x50505050 result[14]=0x01000001

ABS_OFFSET=0x54545454 result[15]=0x01000011

ABS_OFFSET=0x58585858 result[16]=0x01000011

ABS_OFFSET=0x5C5C5C5C result[17]=0x11000011

ABS_OFFSET=0x60606060 result[18]=0x11000011

ABS_OFFSET=0x64646464 result[19]=0x11011111

ABS_OFFSET=0x68686868 result[1A]=0x11111111

ABS_OFFSET=0x6C6C6C6C result[1B]=0x11111111

ABS_OFFSET=0x70707070 result[1C]=0x11111111

ABS_OFFSET=0x74747474 result[1D]=0x11111111

ABS_OFFSET=0x78787878 result[1E]=0x11111111

ABS_OFFSET=0x7C7C7C7C result[1F]=0x11111111

Byte 0: (0x08 - 0x4c), middle value:0x2a

Byte 1: (0x10 - 0x50), middle value:0x30

Byte 2: (0x0c - 0x60), middle value:0x36

Byte 3: (0x08 - 0x60), middle value:0x34

Byte 4:

Byte 5: (0x14 - 0x64), middle value:0x3c

Byte 6: (0x04 - 0x44), middle value:0x24

Byte 7: (0x10 - 0x58), middle value:0x34

MMDC0 MPWRDLCTL = 0x3436302A,MMDC1 MPWRDLCTL = 0x34243C36

   MMDC registers updated from calibration

   Write leveling calibration

   MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00080013

   MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x002B001E

   MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x000D0025

   MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x00000000

   Read DQS Gating calibration

   MPDGCTRL0 PHY0 (0x021b083c) = 0x443C044C

   MPDGCTRL1 PHY0 (0x021b0840) = 0x044C0448

   MPDGCTRL0 PHY1 (0x021b483c) = 0x443C0448

   MPDGCTRL1 PHY1 (0x021b4840) = 0x0434040C

   Read calibration

   MPRDDLCTL PHY0 (0x021b0848) = 0x322C343A

   MPRDDLCTL PHY1 (0x021b4848) = 0x302E2C3C

   Write calibration

   MPWRDLCTL PHY0 (0x021b0850) = 0x3436302A

   MPWRDLCTL PHY1 (0x021b4850) = 0x34243C36

Success: DDR calibration completed!!!

[igorpadykov]

Hi Yongwoo

when boots fails could you attach jtag and check

SRC_SBMR1,2 registers: do they have correct values (set by boot pins)

Best regards

igor

[yongwoolee]

Hi Igor

I check the power sequences with the scope and it is satisfied with the requirement. As I mentioned in the first comment, I am using the "F0" script and the PF0100NPAEP's sequence is matched with it according to my test.

According to our test, it seems that eMMC loads correctly and all the DCDs
register settings are applied properly, the problem starts later on when the
ROM code moves on to initializing the DDRs - if that matters.

When it fails to boot, there is no proper DDR Clock, compared to the normal operation.

As you mentioned, I run the DDR test for 4 DDR3. What does the result mean below?

============================================

        Boot Configuration

SRC_SBMR1(0x020d8004) = 0x00002060

SRC_SBMR2(0x020d801c) = 0x21000011

============================================

ARM Clock set to 1GHz

============================================

        DDR configuration

BOOT_CFG3[5-4]: 0x00, Single DDR channel.

DDR type is DDR3

Data width: 64, bank num: 8

Row size: 14, col size: 10

Chip select CSD0 is used

Density per chip select: 1024MB

============================================

DDR Stress Test Iteration 1

Current Temperature: 60

============================================

DDR Freq: 672 MHz

t0.1: data is addr test

Address of failure: 0x10000004

Data was: 0x00000014

But pattern  should match address

Error: failed to run stress test!!!

[igorpadykov]

Hi Yongwoo

one can recheck power up sequence with oscilloscope and

rerun ddr test for 4 DDR3 case to obtain more accurate calibration

coefficients.

https://community.freescale.com/docs/DOC-105652

Best regards

igor

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