IMX6 IPU's whole picture

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IMX6 IPU's whole picture

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senixsenix
Contributor I

In page 3538 ,Imx6 RM, there are signals like ipu_di0_data(24bit) ipu_di0_hsync  ipu_di0_vsync.

I want to know where they come from?

In page 2831-2832 ,Imx6 RM, there are PINs ipp_di_#_pin11 to ipp_di_#_pin17.

Are these PINs used for data's waveform? what's the connections between the PINs and the ipu_di0_data(24bit)?


as for the asynchronous interface, since the 9 timers determine the control signals,what's the PINs of these signals? And how are they routed?

In RM, there nothing about the connections between  DC&DI, DI&Pins,Pins&othe ip&PAD.

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senixsenix
Contributor I

Does ipu_di0_data(24bit) in page 3538 correspond to IPU1_DISP0_DATA0-23 in page 2712?

how Di send data onto these pins?


Does ipp_di_#_pin11-17 in page 2831-2832 correspond to IPU1_DI0_PIN11-17 in page 2712?

these pins are the data pins? why?


Does the 9 DI timers correspond to IPU1_DI0_PIN01-08 in page 2712?


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qiang_li-mpu_se
NXP Employee
NXP Employee

The signal such as ipu_di0_data, ipu_di0_hsync, ipu_di0_vsync are internal signal, if you set IOMUX registers to IPU_DISP related functions, these signals will be router to IPU_DISP0_DATA0~23 and IPU_DI_PINs.

So you can think these signals are IPU internal output pins, they can be routed to external PAD pins or routed to other internal modules such as HDMI and LVDS.

For IPU_DI0_PIN01~08, they are timing PINs, they can be used to output IPU DI counter 1~8, the DI counter 0 is for pix clock, and DI counter 9 is a special counter, it can't be output to DI pins.

For IPU_DI0_PIN11~17, they are combined with for IPU DC waveform which can be used for some control signal such as Data Enable.

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zaheerm
Contributor I

Can I use DI0_PIN04 for Data Enable?

How can I configure the same?

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qiang_li-mpu_se
NXP Employee
NXP Employee

You can generate timing signal output from DI0_PIN04 and connect it to the LCD to simulate the data enable signal, but the real Data Enable signal will always output from PIN11~PIN17.

From my point of view, the simulated signal output on DI0_PIN04 can be same as real Data Enable signal by programing the DI counter related registers.

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zaheerm
Contributor I

Can you pl. share the details for the same. Which registers to modify and what are the values.

Thanks.

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qiang_li-mpu_se
NXP Employee
NXP Employee

Since the DI counter 4 had already been used in current BSP, it needs modify all IPU DI and DC code to free it for DI_PIN4, I don't have such reference code.

The followed is an example to use DI_PIN6 as Data Enable, in ipu_disp.c:

  _ipu_di_sync_config(ipu, disp,
     6,   //DI_COUNTER 6
     1 - 1,  DI_SYNC_HSYNC,   // The signal referenced to HSYNC, period is 1 HSYNC
     1, DI_SYNC_CLK,  // Offset, the signal will appear after 1 pixel clocks each time
     1, // The signal appears once each time.
     DI_SYNC_HSYNC,  //  The signal restarts with each HSYNC.
     1,  // The signal needs be output from DI_PIN6
     DI_SYNC_NONE,
     DI_SYNC_CLK, 0, (width) * 2);  // The signal keeps high in width pixel clocks.

The Offset, up, down setting can be used to adjust the DI_PIN06 waveform.

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qiang_li-mpu_se
NXP Employee
NXP Employee

For how to re-assign the DI counter and DI PINs, you can reference to this link:

https://community.freescale.com/thread/279078

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