IMX6 DDR3 Stress test and DRAM layout

jiyoonchung · ‎06-03-2015

Hi

We modified Sabresd board, but DDR Stress test was passed at 475MHz.

At 500MHz or 528MHz, writing level calibration seems odd and boards were failed at 500MHz or 525MHz.

Currently we are using IMX6D (dual core).

See below.

MMDC_MPWLDECTRL0 ch0 after write level cal: 0x0013000F

MMDC_MPWLDECTRL1 ch0 after write level cal: 0x00150013

MMDC_MPWLDECTRL0 ch1 after write level cal: 0x00040013

MMDC_MPWLDECTRL1 ch1 after write level cal: 0x017F000A

In 475MHz, MMDC_MPWLDECTRL1 ch1 was 0x0001000B, but it changed to 0x017F000A.

We are planning to revise board soon. Do you have any idea to resolve this matter and achieve 528MHz or higher?

Is there any restriction on number of vias?

Or, variation of length of trace?

Thanks in advance.

James

jiyoonchung · ‎06-05-2015

I checked length of signals to DDR3. Some of them are longer than clock.

I fixed the problem by increasing clock path.

igorpadykov · ‎06-04-2015

Hi JI

Please check IMX6DQ6SDLHDG Chapter 3

i.MX 6 Series Layout Recommendations

One can try to use WALAT = 1 in memory initialization script,

also recommended tweak drive strengths - please refer to section 2.1.3 SI '[(Signal Integrity)

Consideration] of the "Freescale i.MX6 DRAM Port Application Guide-DDR3.pdf"

Best regards

igor

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