Hello,
We are using imx6 (cortex- A9) board with the following configuration
CPU configuration :
Cores enabled : one
DDR3 Clock : 528MHz
ARM Core clock : 996MHz
mmu configuration for ARM:
mmu - enabled
L1 data cache - enabled
L1 instruction cache - enabled
D-side prefetch - enabled
Branch prediction - enabled
L2 cache - disabled
We also used DDR calibration data from the sabre board sdk. With the above configuration system is not stable. The system works only when ARM core clock is reduced to 900 MHz. We are not able to increase the ARM core clock from 900MHz to 996Mhz.
We again, calibrated the DDR using the stress test tool, with the following configuration for the device and the system.
Input provided through GUI :
DDR frequency : 528Mhz
MR Value(Hex) : 0004
Device Information
Manufacturer : Micron
Memory part number : MT41K256M16HA-125 XIT:E
Memory type : DDR3-1600
DRAM density (Gb) 4
DRAM Bus Width 16
Number of Banks 8
Number of ROW Addresses 15
Number of COLUMN Addresses 10
Page Size (K) 2
Self-Refresh Temperature (SRT) Normal
tRCD=tRP=CL (ns) 13.75
tRC Min (ns) 48.75
tRAS Min (ns) 35
System Information
i.Mx Part i.Mx6D
Bus Width 64
Density per chip select (Gb) 16
Number of Chip Selects used 1
Total DRAM Density (Gb) 16
DRAM Clock Freq (MHz) 528
DRAM Clock Cycle Time (ns) 1.894
Address Mirror (for CS1) Disable
SI Configuration
DRAM DSE Setting - DQ/DQM (ohm) 48
DRAM DSE Setting - ADDR/CMD/CTL (ohm) 48
DRAM DSE Setting - CK (ohm) 48
DRAM DSE Setting - DQS (ohm) 48
System ODT Setting (ohm) 120
With the above configuration system is still not stable, when ARM core clock is set to 996MHz. The system works only when ARM core clock is reduced to 900 MHz. We are not able to increase the ARM core clock from 900MHz to 996Mhz.
Kindly find attached the script file, which is used to calibrate the DDR.
Thanks,
Gopu
Original Attachment has been moved to: DDR_Script.inc.zip
