IMX6: Clocks Alignment of LVDS Output in Split Mode

[dalain00]

Hi,

I look at the datasheet and inside the PRM of the IMX6: no luck! I would like to know if both LVDS clocks of both ports will be aligned in split mode? Or do I need to deal with some shift inside my FPGA? In other words, can I use only the clock of port0 for both LVDS ports?

Thanks,

Denis Alain, Eng. 

[dalain00]

Hi Artur,

Thanks for the info. I will ask the SW Eng. to configure the clock that way.

Best Regards, 

Denis.

[art]

To make me able to provide you with the accurate answer, first, please specify, which exactly member of the i.MX6 family processors do you mean.

Best Regards,
Artur

[dalain00]

Hi Artur,

We want to design two different products. One with the IMX6S (MCIMX6S5EVM10AC) and another with the IMX6D (not the dual lite). The exact part number of the dual has not been confirmed yet. Do you need this info to confirm the alignment?

Thanks,

Denis Alain, Eng.  

[art]

To operate in split mode, the clocks for both LVDS channels should be configured to have the same root clock inside the Clock Controller module. Of course, in that case, the serial clocks for both LVDS channels will be aligned. For more information, please refer to the Chapter 18 "Clock Controller Module" of the corresponding Reference Manual documet, that can be found on the corresponding processor's Documentation web page.

For i.MX6Dual:

http://www.nxp.com/products/automotive-products/microcontrollers-and-processors/arm-mcus-and-mpus/i....

For i.MX6Solo:

http://www.nxp.com/products/automotive-products/microcontrollers-and-processors/arm-mcus-and-mpus/i....

Have a great day,
Artur

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[_at]

art‌

Hi Artur Petukho,

Same kind of question from me.

I have 1920x720 LVDS panel and add "split-mode" in dtsi of i.mx6.

LVDS panel says: 1920x720 @ 60 = 47.5 Mhz.

Is any limitation of  split-mode (odd/even) with resolution on IMX6?

Can you explain IPU DI0 clock settings and LVDS CH0/CH1 serialize clock settings for split-mode ?

The below settings is not functional:

• IPU1 DI0 clock = 47.5 MHz, LDB CH0 serialzer clock = 166 MHz.
• Screen is not synchronized to full 1920x720 panel

//// **  Not functional *** /////

&ldb {
status = "okay";
split-mode;

lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
primary;
status = "okay";

display-timings {
native-mode = <&timing0>;
timing0: C123HAN021 {
clock-frequency = <47500000>;
hactive = <1920>;
vactive = <720>;
hback-porch = <20>;
hfront-porch = <40>;
vback-porch = <20>;
vfront-porch = <10>;
hsync-len = <20>;
vsync-len = <10>;

};

};

};

};

The below settings functional but with limitation

• Screen synchronized to full 1920x720
• But 1/3 portion of screen's color is not proper RGB
• 2/3 portion of screen is proper RGB
• IPU1 DI0 clock = 142.5 MHz, LDB (CH0 serialzer clock) = 498 MHz.

//// **  functional with color limitation*** /////

&ldb {
status = "okay";
split-mode;

lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
primary;
status = "okay";

display-timings {
native-mode = <&timing0>;
timing0: C123HAN021 {
clock-frequency = <142500000>;
hactive = <1920>;
vactive = <720>;
hback-porch = <20>;
hfront-porch = <40>;
vback-porch = <20>;
vfront-porch = <10>;
hsync-len = <20>;
vsync-len = <10>;

};

};

};

};

Please help us to resolve this.

-Ankit.