IMX6 CCM control from device tree

[chrisroed]

 I'm trying to configure an LDB display.  I'm noticing a discrepancy in what I set as the clock-frequency and what is actually done.

In my device tree, I specify these values.

/* LVDS data bridge */
&ldb {
  status = "okay";

  lvds-channel@0 {
    fsl,data-mapping = "spwg";
    fsl,data-width = <24>;
    status = "okay";
    crtc = "ipu1-di0";
    primary;

    display-timings {
      native-mode = <&timing0>;
      timing0: display0 {
        clock-frequency = <71980800>;
        hactive = <800>;
        hback-porch = <24>;
        hfront-porch = <72>;
        hsync-len = <24>;
        vactive = <1280>;
        vback-porch = <10>;
        vfront-porch = <12>;
        vsync-len = <2>;
      };
    };
  };
};

The problem is that when I actually use this device tree, the clock is NOT set according to `clock-frequency`

root@imx6dl:~# cat /sys/kernel/debug/clk/clk_summary | grep ldb
    ldb_di0_sel                 1            1   396000000          0 0  
        ldb_di0_div_7           0            0    56571428          0 0  
            ldb_di0_div_sel     0            0    56571428          0 0  
        ldb_di0_div_3_5         1            1   113142857          0 0  
            ldb_di0_podf        1            1    56571429          0 0  
                ldb_di0         1            1    56571429          0 0  
    ldb_di1_sel                 0            0   396000000          0 0  
        ldb_di1_div_7           0            0    56571428          0 0  
            ldb_di1_div_sel     0            0    56571428          0 0  
        ldb_di1_div_3_5         0            0   113142857          0 0  
            ldb_di1_podf        0            0    56571429          0 0  
                ldb_di1         0            0    56571429          0 0  

I have tried modified the `clock-frequency` variable in the device tree higher and lower with no success.  I realized that these clocks are generated from PLLs and and in order to get the correct frequency I need to modify the "CS2CDR" register in the CCM.  I'm not sure where to do this... 

I don't need to change the pll once I'm running, so my ideal situation would be that I set it in the devicetree or on boot (or u-boot) and not worry about it anymore.

What is the appropriate way to make this selection?

[chrisroed]

After some digging, I discovered that there is a way to set the LDB clocks from the device tree.  Just for the record, I'm using kernel source from yocto sumo, 4.9.88 ( https://source.codeaurora.org/external/imx/linux-imx/log/?h=imx_4.9.88_2.0.0_ga )

In your device tree you can change the assigned parent clocks (only for ldb) with this code.   

&clks {
    assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
        <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
    assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
	<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
};

I need to do some more research on the implications of this, as it seems to have messed with both my uart terminal and my GPU clock at the very least.

Edit:  There was no problem with the GPU clock.  The yocto version that I was using built a different version of the vivante module than is in the kernel source.  I just grabbed that code to compile the newer version.  I never figured out why this messed with the UART clock though

[igorpadykov]

Hi Chris

may be useful below

https://community.nxp.com/t5/i-MX-Processors/LVDS-pixel-clock-on-i-MX6/m-p/289733

EB821  LDB Clock Switch Procedure & i.MX6 Asynchronous Clock Switching Guidelines

Best regards
igor

[chrisroed]

Yes, I understand that the PLL clock parent needs to be changed.  What I'm asking is *where* do I make that change?

Can I change it in the device tree?  (this is ideal)

Can I change it in u-boot?

Do I need to modify the kernel?  If so, do I need to modify the clock setup ( drivers/clk/imx/clk-imx6q.c) or do I modify the ldb driver ( drivers/video/fbdev/mxc/ldb.c) or is there some other place to make the change?

[igorpadykov · Accepted solution]

>What I'm asking is *where* do I make that change?

on suggested link it is done in clock driver (clk-imx6q.c), also please look at attached patch :

https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/clk/imx/clk-imx6q.c?h=lf-5.10.y

https://community.nxp.com/t5/i-MX-Processors/LVDS-pixel-clock-on-i-MX6/m-p/289733

 

Best regards
igor

[chrisroed]

@igorpadykov can you tell me what version of the kernel that patch is for?

[igorpadykov]

https://dev.sigmadrone.org/sigmadrone/linux-colibri/commit/eecbe9a52587cf9eec30132fb9b8a6761f3a1e6d

Best regards
igor

[krishna_b]

I'm also facing the same issue. I have set clock frequency 71Mhz in device tree but I'm getting 37 mhz at out display output. I'm also using imx6 quad only