I was wondering if there was a way to invert the MDC of the fsl-fec Ethernet controller via a setting in the DTS file?
Looking at the data sheet for the LAN8720 ethernet tranceiver datasheet: http://media.digikey.com/pdf/Data%20Sheets/SMSC/LAN8720.pdf
pgs 35/55 it look like the Data should be clocked in on the rising edge of the MDC signal. With at least 10ns of setup/hold
However when I look at the two signals on a scope, I can see that this timing requirement is not met (looks like both MDIO and MDC are changing at the same time)
So I was wondering if there was any way of inverting it via the .dts file to improve the margin?
I'm using Kernel 3.12,
Same image on EVK as my custom board (same pins for the ethernet controller etc.)
I'm using yocto to build the image, but I'm not very experienced with it, so I'd struggle to build and deploy a different U-Boot wihtout any pointers?
I've ordered up a USB-UART dongle so I can see what is going on via the debug port (previously I've just SSH's through the ethernet port, but I can't do this obviously).
How would I test the Ethernet Port just using U-Boot?
Looking at the signals, it looks like everything starts up okay, But the first burst of activity on the MDIO is shorter than on the EVK, Also the EVK has regular activity on the MDIO, but my board does not.
The MDC is running at all times on both boards.
Once I get the debug dongle I'll be able to get some more info I hope. I'm pretty certain it's a hardware issue, it could even be a completely unrelated part of the design....
Run the following in the U-Boot command line:
setenv ipaddr 192.168.1.300
setenv netmask 255.255.255.0
Where 192.168.1.300 is the boards' IP address and .301 is the remote machines' IP address . If the 'ping' command passes , then your ethernet works .
Okay, so I feel a bit foolish now.
Turns out my leds start blinking during boot but the boot doesn't complete.
The board is hanging when it tries to load rootfs, I've created another thread:
And I'll close this if the solution to that fixes it.
Should have got my boss to stump up for a serial cable earlier.
I have multiple i.MX28 designs with LAN8720A PHY and the MDIO/MDC lines are connected directly to the CPU in all the schematics. There is but one more passive component and that is a 1K5 pullup resistor between MDIO and +3V3 lines. The MDIO interface works as expected.
I am delighted that you don't have any issues with your IMX28 designs.
The Hardware I am looking at is also connected directly between the PHY and the processor with a 1k5 resistor on the open drain io line.
I'm running the same image on an IMX28_evk as well as my custom hardware, but the ethernet controller works on one board (evk) but not the other. Looking at the timing, it is marginal on both boards, so I wanted to exclude this from my investigation.
With marginal timing parameters there could be a number of contributing factors that affect succesful timing, like minor differences in supply voltages and biases, extra capacitance on the signal lines, noise etc.
If there was a way to adjust the timing of the ip_block it would save me a lot of time and investigation.
You're right, the MX28EVK also uses the SMSC 8720A PHYs.
Let's check why your ethernet doesn't work.
-> What version of U-Boot and Linux do you use ?
-> Does this not work in U-Boot or Linux or both ?
Can you try mainline U-Boot 2014.01 for mx28evk ? I use that on my MX28EVK without any issues. It should be easy for you to try I hope.
You don't need any special tools to build a working image of U-Boot 2014.01 (not even elftosb :smileyhappy: ), just the toolchain.