IDMAC CH23 and CH27 double buffering issue in i.MX6 S

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IDMAC CH23 and CH27 double buffering issue in i.MX6 S

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suryag
Contributor II

  

Hi,

We want to use double buffer mode for IDMA CH23 and CH27 channels in i.MX6 S. We are selecting the double buffer mode by setting ch23 and ch27 corresponding bits in IPU_CH_DB_MODE_SEL0 register.

But only EBA1 memory data  only appearing on LCD and EBA0 memory data is not  appearing on LCD

Could you please suggest anyone, is any other settings are required for enabling the double buffer mode.

Thanks & Regards

SuryaG

+91- 8904410511

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Yuri
NXP TechSupport
NXP TechSupport

Basically double buffering approach may be used for any IDMAC channel.
But, please pay attention, system requires synchronization (to avoid hanging),
as described in section 37.4.12.2.2 (Frame Synchronization Flow) of the i.MX6 DQ

Reference Manual. In  particular – item 3 (Triggering).

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