I2S clock on I.MX6DL

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I2S clock on I.MX6DL

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Contributor II

Hi,   

I have two questions about I2S on I.MX6DL.

(a)

Currently, we plan to use SoC as I2S master mode, and assigned function for each pad to connect I2S signals to external codec as below.

pastedImage_6.png

In hardware connection point of view, this I2S signal connection is correct?, and work as normally?

(b)

Is it possible to set CCM configuration to provide the same clock source to SSI's sys and CCM_CLKO1?

Br,

Yuji

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Contributor II

Hi, Igor

(1)OK.

(2)Thank you.

   Providing MCK from CCM_CLKO1 , or from aud4_rxc, there are any difference for I2S function?

Br,

Yuji

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NXP TechSupport
NXP TechSupport

Hi Yuji

1. yes connection is correct.

2. >Is it possible to set CCM configuration to provide the same clock source to SSI's sys and CCM_CLKO1?

in  general no. To achieve it one can try to choose appropriate settings (register dividers)

described in sect.18.6.21 CCM Clock Output Source Register (CCM_CCOSR) and

sect.61.8.4.1 SSI Clock and Frame Sync Generation

i.MX 6Solo/6DualLite Applications Processor Reference Manual

Best regards
igor
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