I use the 50M clock generated by the CPU to provide the working clock for the PHY RMII interface,but I used a power-on reset to reset the PHY and CPU at the same time，not a GPIO reset.Thousands of boards which use the on chip clock generator, are currently produced, and the work is quite stable. but in the document IMX6DQ6SDLHDG，on the page 109，the schematic notes that PHY_ RESET_B must be a GPIO toggled after CLKIN is active.
My question is How big the risk of network disconnection due to the wrong reset and clock sequence? My client wants to know How big is the risk .
Now that the circuit board card reserves the position of the external 50M clock crystal oscillator for the phy, is it necessary to change to an external crystal oscillator to reduce the risk of network failure without redesigning the circuit board.
Looking forward to your reply！
