I cannot find the PF0100F3 PMIC, is it really necessary for the iMX6SL?

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I cannot find the PF0100F3 PMIC, is it really necessary for the iMX6SL?

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nathanpalmer
Contributor IV

I have been waiting for months for the F3 version of the PF0100 PMIC to become available for the iMX6SL but it is too late to wait any longer.  I understand that the F3 version of the PF0100 PMIC is like the F1 version but the power sequence is slightly modified to fix an errata on the iMX6SL.  I cannot find the MMPF0100F3A available anywhere so I am considering the NP or the F1 versions.  I would prefer to use the F1 version because it seems to be available from multiple vendors.  What is the nature of the errata that the F3 version fixes?  I need to way the risk of using the F1 version versus the extra labor to manually program the NP version.

[Edit]

I guess I don't have to get the NP version of the chip, the F1 version can be programmed to use OTP correct?

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Nathan

regarding "nature of the errata that the F3 version fixes"-

F3 changed power-up sequence, making VDDHIGH power-up first

(or immediately after VSNVS). Without this, during power up

there may be a drop in the VSNVS voltage, violating the processor power-up sequence.

Explanation of such behaviour may be found in

IMX6SLHDG Hardware Development Guide for i.MX 6SoloLite - User Guide,

Table 1-6 "Power and decouple recommendations",

"Do not overload coin cell backup power rail VDD_SNVS_IN" :

"When VDD_SNVS_IN > VDD_HIGH_IN,

VDD_SNVS_IN supplies current to SNVS, and some

current flows into VDD_HIGH_IN."

This situation may happen when first applied VDDARM,VDDSOC or others

supplies and later VDD_HIGH_IN. In this case small leakage voltage on

VDD_HIGH_IN may cause current flow from VDD_SNVS_IN, thus causing it to

enter current limitation, that causes a drop in the VSNVS voltage.

Note, securely grounded VDD_HIGH_IN can not cause this effect.

Another benefit is that powering first VDDHIGH power, allows more

time for starting-up 24MHz oscillator. Since it is powered from VDDHIGH_IN.

as described in Figure 36-1 "Power system overview"

IMX6SLRM i.MX 6SoloLite Applications Processor Reference Manual.

Regarding "F1 version can be programmed" to another option - not sorry.

One needs to program fresh not-programmed part.

Best regards

chip

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Nathan

regarding "nature of the errata that the F3 version fixes"-

F3 changed power-up sequence, making VDDHIGH power-up first

(or immediately after VSNVS). Without this, during power up

there may be a drop in the VSNVS voltage, violating the processor power-up sequence.

Explanation of such behaviour may be found in

IMX6SLHDG Hardware Development Guide for i.MX 6SoloLite - User Guide,

Table 1-6 "Power and decouple recommendations",

"Do not overload coin cell backup power rail VDD_SNVS_IN" :

"When VDD_SNVS_IN > VDD_HIGH_IN,

VDD_SNVS_IN supplies current to SNVS, and some

current flows into VDD_HIGH_IN."

This situation may happen when first applied VDDARM,VDDSOC or others

supplies and later VDD_HIGH_IN. In this case small leakage voltage on

VDD_HIGH_IN may cause current flow from VDD_SNVS_IN, thus causing it to

enter current limitation, that causes a drop in the VSNVS voltage.

Note, securely grounded VDD_HIGH_IN can not cause this effect.

Another benefit is that powering first VDDHIGH power, allows more

time for starting-up 24MHz oscillator. Since it is powered from VDDHIGH_IN.

as described in Figure 36-1 "Power system overview"

IMX6SLRM i.MX 6SoloLite Applications Processor Reference Manual.

Regarding "F1 version can be programmed" to another option - not sorry.

One needs to program fresh not-programmed part.

Best regards

chip

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

View solution in original post

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nathanpalmer
Contributor IV

I was finally able to order the F3 parts so I think we are OK.  However, as a backup I still ordered some NP parts and a programmer as well. 

One last question on this subject:  Can I read the PF0100-F3 OTP configuration to a file and then write that configuration to a PF0100-NP device?  Basically, clone the F3 in case I cannot order them in the future.  The PF0100 Programmer GUI implies that I can but I don't have the parts to try the experiment.

Thanks for all of the help!

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nathanpalmer
Contributor IV

Thanks for the explanation.   I guess I need to use the NP version of the PMICs and program to match the P3 configuration.  I see that there is not a script or a preset config file for the KITPFGUI 4.0.0.14 Programmer Utility to program an NP part to be a P3 part.  I see configs for P0, P1, and P2 but not for P3 and P4.  I Understand that the P3 is very similar to the P1, but I would like to minimize risk and use the EXACT same configuration as the P3 so that in the future we can swap in the P3 for the NP if the become available.

Do you have access to a PF0100_P3.cfg file for the KITFPGUI tool?

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