HI,
I am facing an issue , Not able to see any data on the TXD pin of the processor line during ping command from Uboot and I am getting below message
____________________________________
ARP Retry count exceeded; starting again
ping failed; host 192.168.36.136 is not alive
_________________________________________
I am using DP83848 PHY IC in I.MX8MM custom board, Following are my configuration for RMII Mode. Do let me know the correct configuration to solve my issue
1. In fsl-imx8mm-evk.dts
--------------------------------------------------------------------------------------------------------------------------
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f /*ENET_TD2 OR REF_CLK Ref 1489 softwaredatasheet*/
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
/*MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19*/ /*Use this for NXP EVK - Commented by santhosh */
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 /*LVDS board RESET_ETH*/
>;
};
--------------------------------------------------------------------------------------------------------------------------
2. in imx8mm_evk.h the changes is as below
--------------------------------------------------------------------------------------------------------------------------
#define CONFIG_ETHPRIME "FEC"
/* Configuration for RMII*/
#define CONFIG_FEC_MXC
#define FEC_QUIRK_ENET_MAC
#define IMX_FEC_BASE 0x30BE0000
#define CONFIG_PHYLIB
#define CONFIG_FEC_XCV_TYPE RMII
/*#define CONFIG_PHY_REALTEK*/
#define CONFIG_PHY_NATSEMI
#define CONFIG_FEC_MXC_PHYADDR 0//3
#define CONFIG_NET_RANDOM_ETHADDR
#if 0
#define CONFIG_FEC_MXC
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 0
#define FEC_QUIRK_ENET_MAC
#define CONFIG_PHY_GIGE
#define IMX_FEC_BASE 0x30BE0000
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
#endif
#endif
--------------------------------------------------------------------------------------------------------------------------
3. In imx8mm_evk.c made the chage as below
--------------------------------------------------------------------------------------------------------------------------
static int setup_fec(void)
{
debug("LVDS:setup_fec\n");
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
/*
* GPR1 bit 13:
* 1:enet1 rmii clock comes from ccm->pad->loopback, SION bit for the pad (iomuxc_sw_input_on_pad_enet_td2) should be set also;
* 0:enet1 rmii clock comes from external phy or osc
*/
// added by santhosh for RMII mode for LVDS hardware board
#if 1
debug("setup_fec\n");
setbits_le32(&iomuxc_gpr_regs->gpr[1],
//IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT); //working
IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK); //working
return set_clk_enet(ENET_50MHZ); //
#endif
// RGMII mode Commented by santhosh
#if 0
setup_iomux_fec();
/* Use 125M anatop REF_CLK1 for ENET1, not from external */
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0);
return set_clk_enet(ENET_125MHZ);
#endif
}
--------------------------------------------------------------------------------------------------------------------------
This are the changes done and in uboot i am doing
setenv ipaddr 192.168.36.126
setenv serverip 192.168.36.101
setenv netmask 255.255.255.0
setenv gatewayip 192.168.36.1
setenv ethaddr 10:7d:1a:43:21:0c
setenv ethact ethernet@30be0000
setenv ethprime FEC
saveenv
