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I.MX7 power sequencing

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I.MX7 power sequencing

‎10-04-2021 10:18 AM
1,920 Views
NIKHITHAANTONY
Contributor I

In the datasheet of I.MX7 it is given that, VDD_SOC should powerup before NVCC_DRAM and NVCC_DRAM_CKE. So whether it can be done by software. In hardware design, whether we need to take care anything for delaying NVCC_DRAM and NVCC_DRAM_CKE

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‎10-04-2021 10:19 PM
1,902 Views
NIKHITHAANTONY
Contributor I

Then How VDD_SOC will become high before NVCC_DRAM and NVCC_DRAM_CKE.

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‎10-04-2021 11:56 PM
1,896 Views
igorpadykov
NXP Employee
NXP Employee

>How VDD_SOC will become high before NVCC_DRAM and NVCC_DRAM_CKE

 

in hardware. Use appropriate PMIC with power-up sequence compatible with i.MX7D datasheet

requirements.

 

Best regards
igor

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‎10-05-2021 02:04 AM
1,888 Views
NIKHITHAANTONY
Contributor I

We designed I.MX7 processor as per SABRE board. In that PMIC PF3000 is used. 

So there will be correct power sequencing..right?

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‎10-05-2021 02:49 AM
1,883 Views
igorpadykov
NXP Employee
NXP Employee

>We designed I.MX7 processor as per SABRE board. In that PMIC PF3000 is used. 

>So there will be correct power sequencing..right?

 

right

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‎10-04-2021 05:09 PM
1,908 Views
igorpadykov
NXP Employee
NXP Employee

Hi NIKHITHA

 

>whether it can be done by software..

 

no

 

>whether we need to take care anything for delaying NVCC_DRAM and NVCC_DRAM_CKE

 

no need.

 

Best regards
igor

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