CCGR6 is enabled. I have also enabled CCM_ANALOG_PLL_USB1 according the procedure by NXP document:
1. Enable PLL.
2. Set POWER bit to power-up the PLL.
3. Wait for PLL_LOCK bit to assert.
4. Clear BYPASS bit. This will switch the PLL output from Bypass clock to PLL output clock.
5. Set EN_USB_CLKS. This enables the PLL’s 9-phase clock output for the PHY
It is still not working.
I always cycle power before loading by JTAG. So I think the i.MX6UL bootrom code runs first and initialize the USB as a HID device. My code then reinitialize the USB to another device. I guess the bootrom code help me some how. When configured to boot from QSPI, the bootrom loads code from QSPI and never initialize the USB.
