I.MX6DQRM parallel display DI0_DISP_CLK signal level

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I.MX6DQRM parallel display DI0_DISP_CLK signal level

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Contributor I


Dear ALL

I test I.MX6DQRM Parallel Display in sabre board.

I have a problem in parallel display interface clock level.

DI0_DISP_CLK' hw signal level is just 0.8V, it has DC offset about 1.3V.

Almost every output signal is operating in 0V ~ 3.3V, but DI0_DISP_CLK output clock is 0.8V.

How can I get normal DI0_DISP_CLK output clock?

I want to get 108Mhz, 3.3V DI0_DISP_CLK parallel output clock.

What I have to set?

Plz help reply.....

Thanks..

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NXP TechSupport
NXP TechSupport

Hi younggeun

"DC offset about 1.3V" may mean that this pin is damaged or connected with other output signal.

One can try to attach jtag and configure pin as gpio, try to toggle it. For testing may be useful

baremetal sdk (zip can be found on https://community.nxp.com/thread/432859 ), it has jtag scripts and baremetal ipu tests.

Best regards
igor
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