Hi,
I am using I.Mx6 (MCIMX6Q6AVT10AD) with 4 Dram Chip (MT41K256M16TW-107 AAT:P). each has 256MB.(Total 1GB DDR). in one of my current project.
U3-> Processor (I.mX6)
U4,U5,U6,U7 - > DRAM Chips
I have doubt in the I.MX6 hardware deisgn guide for DDR3 clock Routing please clarify on this.
In that Clock length max mentioned 2.25inches.
is it for Overall clock length should be ≤ 2.25 inches for "T" topology should consider or point to point (Processor to DRAM) should be ≤ 2.25inches in same "T Topology"?
I have lenght matched as follows:
1. from processor to U4 the Trace path 1,2,3 - 2.138 inches (SDCLK1)
2. from processor to U5 the Trace path 1,2,4 - 2.140 inches (SDCLK1)
3. from processor to U6 the Trace path 1,5,6 - 2.138 inches (SDCLK0)
4. from processor to U7 the Trace path 1,5,7 - 2.140 inches (SDCLK0)
But the overall etch length shows 2.47 Inches ( includes termination resistors).
clock with Address , cmd, cntl -> ( 50 mils), (Segmentwise "T" lenght matched).
within address group ->(25mils).(Segmentwise "T" lenght matched).
Differential clock -> 3mils
Data and Strobe -> 5mils,
Differential data storbe -> 5mils.
Clock and datastrobe -> (- 800mils). datastobe length ->1300mils.
please clarify on that. we are in board release phase for production.
Best Regards,
Mohamed A S.
