Hello,
I need use 5 CSs to configure CS0(64MB), CS1(32MB), CS2(32MB), CS3(32MB), CS4(32MB) in i.MX502 based system.
In the IMX50RM the page 150, it says,
Off Chip Memories
The supported configurations are
• CS0(128M), CS1 (0M), CS2 (0M),CS3(0M)
• CS0(64M), CS1(64M), CS2(0M), CS3(0M)
• CS0(64M), CS1(32M), CS2(32M),CS3(0M)
• CS0(32M), CS1(32M), CS2(32M),CS3(32M)
However in the latter page, in the "23.2 Featrus".
It says:
• Up to four chip selects for external devices
• Flexible address decoding. Each chip select memory space determined separately, according to VIA port configuration (see Chip Select Memory Map).
Configurable Chip Select 0 base address (by VIA)
• Individual select signal for each one of the memory space defined. Up to 6 memory spaces may be defined and programmed individually.
• 128-bit external address bus, max memory size can be 256MByte (2 Gigabit).
Seems like max 6 memory spaces with 256MB might be possible.
Is it really possible?
Best regards,
Nori Shinozaki
Solved! Go to Solution.
Hi Nori
correct description is given in page 150 -
this is specific i.MX50 implementation of EIM module, while
sect 23.2 Features gives generic description of EIM
module.
Best regards
igor
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Hollo Igor,
Thank you, I'm planing to increase a CS by adding external logic.
I couldn't find EIM's max fan-out number in the datasheet.
Can i.MX502 fanout total 5 CSs?
Best regards,
Nori Shinozaki
Hi Nori
i.MX50 has CSn described on page 150, seems
one can add some logic for additional "fan-out number".
Best regards
igor
Igor,
Thanks, I read this description.
But not sure about the max fan-outs from the DC characteristics stand point.
Best regards,
Nori Shinozaki