In free-scale solo board,2 DDR RAMs placed in the board. While optimizing power , we tried to test to put the DDR into self refreshing mode. But I cant create a scenario ,where I can see the self-refresh mode enabled bit in MMDC Control and status register (25 bit) ..Need assistance in how to test the working of self refresh mode..
Thank you.
Hi prakeerthi
there is no one bit settings and entering self-refresh mode is performed
during procedure described in sect.44.4.6.2 Self refresh and Frequency change
entry/exit i.MX6DQ Reference Manual
http://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf
One can check with oscilloscope signals described here.
Best regards
igor
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