FAQs
English (US) 日本語 | Japanese 中文 | Chinese (Simplified)

How to use the 88W9098 SDIO mode normally and the pci bus can be used by other devices

cancel
Turn on suggestions
Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type.
Showing results for 
Show  only  | Search instead for 
Did you mean: 

How to use the 88W9098 SDIO mode normally and the pci bus can be used by other devices

‎12-25-2022 08:21 PM
1,279 Views
lanchanning
Contributor II

 

Some questions about IMX8mp WIFI/BT module 88W9098

I am a module using AW-XM458 SDIO mode

kernel version 5.15.32

After the system is started, the wifi driver pre-programmed by yocto can work normally

insmod /lib/modules/5.15.32-lts-next+gfa6c3168595c/extra/mlan.ko
insmod /lib/modules/5.15.32-lts-next+gfa6c3168595c/extra/moal.ko mod_para=nxp/wifi_mod_para.conf

But this driver supports SDIO and PCIE at the same time, so the DTS setting will disable PCIE for the driver to use
Referring to imx8mp-evk-usdhc1-m2.dts can make SDIO work normally!

But it will make PCIE unusable.

May I ask how to modify it so that the PCIE BUS can be used for other PCI devices???

 


1. Refer to  imx8mp-evk-usdhc1-m2.dts setting, you can start SDIO WIFI normally, but it will make PCI BUS unusable


#if WIFI_SDIO_EN
/ {
usdhc1_pwrseq: usdhc1_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;

status = "ok";
};
};

&iomuxc {
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x19
MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x1c4
>;
};

pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x19
MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x1c4
>;
};

pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x19
MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x1c4
>;
};
};

 

 

#if 1
&pcie {
status = "disabled";
/delete-node/ wifi_wake_host;
};

&pcie_phy {
status = "disabled";
};
#endif

 


&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
keep-power-in-suspend;
non-removable;
wakeup-source;
mmc-pwrseq = <&usdhc1_pwrseq>;
fsl,sdio-async-interrupt-enabled;
status = "okay";

wifi_wake_host {
compatible = "nxp,wifi-wake-host";
interrupt-parent = <&gpio2>;
interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "host-wake";
};
};

#endif

 

2. After enabling PCIE, the PCI BUS can be used but the SDIO WIFI cannot be used. 

#if 0
&pcie {
status = "disabled";
/delete-node/ wifi_wake_host;
};

&pcie_phy {
status = "disabled";
};
#endif

 

root@imx8mpevk:~# insmod /lib/modules/5.15.32-lts-next+gfa6c3168595c/extra/mlan.ko
t+gfa6c3168595c/extra/moal.ko mod_para=nxp/wifi_mod_para.conf

[ 106.477000] mlan: loading out-of-tree module taints kernel.
root@imx8mpevk:~# insmod /lib/modules/5.15.32-lts-next+gfa6c3168595c/extra/moal.ko mod_para=nxp/wifi_mod_para.conf
[ 106.546570] wlan: Loading MWLAN driver
[ 106.550924] wlan: Register to Bus Driver...
[ 106.555246] wlan: Register to Bus Driver Done
[ 106.559644] wlan: Driver loaded successfully

 

 

 

 

0 Kudos
Reply
1 Reply

‎12-30-2022 01:57 AM
1,257 Views
lanchanning
Contributor II
see imx8mp-evk-usdhc1-m2.dts 
/ {
      usdhc1_pwrseq: usdhc1_pwrseq {
            compatible = "mmc-pwrseq-simple";
            reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
      };
};
 
&iomuxc {
      pinctrl_usdhc1: usdhc1grp {
            fsl,pins = <
                  MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK    0x190
                  MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD    0x1d0
                  MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0      0x1d0
                  MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1      0x1d0
                  MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2      0x1d0
                  MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3      0x1d0
                  MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06  0x19
                  MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09  0x1c4
            >;
      };
 
MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06  , This seems to conflict with pcie's pin 
EVB  SD1_DATA4 is connect to PCIE 
&pcie{
      pinctrl-names = "default";
      pinctrl-0 = <&pinctrl_pcie>;
      disable-gpio = <&gpio2 6 GPIO_ACTIVE_LOW>;
      reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
.....
 
lanchanning_0-1672390449006.png

 

 
 
 
I modify dts..
/ {
      usdhc1_pwrseq: usdhc1_pwrseq {
            compatible = "mmc-pwrseq-simple";
            //reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
            reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
            status = "ok";
      };
};
 
&iomuxc {
      pinctrl_usdhc1: usdhc1grp {
            fsl,pins = <
                  MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK          0x190 //M2_SD_CLK
                  MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD          0x1d0 //M2_SD_CMD
                  MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0      0x1d0 //M2_SD_DATA0
                  MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1      0x1d0
                  MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2      0x1d0
                  MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3      0x1d0
 
                  //MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06      0x19
                  MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10      0x41  //M2_SD_nRST
 
                  MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08  0x1c4 //M2_BT_WAKE_HOST
                  MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09  0x1c4 //M2_SD_WAKE_HOST
 
            >;
      };
............................................
 
pcie not need disable
&pcie {
      //status = "disabled";
      /delete-node/ wifi_wake_host;
};
 
SDIO can be recognized without modifying the pre-programmed WIFI driver, and PCIE BUS can also be used
0 Kudos
Reply