I want to use the SATA block DAC of imx6Q ,according to "53.5.2.4.6 Analog DC Test Capabilities" of 《i.MX_6Quad_6Dual_Reference_Manual_(Rev_D)》,and "Figure 53-14. High-Level Map of ATB " , I want to make the DAC output through atb_s_p out to Txm, so i make the driver.now the driver can read and write the 16bit reg. But the Txm allways be 0 voltage. What worrng with me ,my partial drivers code as bellow. my_hpriv->plat_data = imxpriv; ret = clk_prepare_enable(imxpriv->sata_clk); if (ret) return ret; ret = imx_sata_enable(my_hpriv); // the clk and sata port can set rightly staticintwrite_inter_DAC(int xx2) { //1.abb_en lane0_RX_ANA_CONTROL_data=read_16reg_data(lane0_RX_ANA_CONTROL_addr); lane0_RX_ANA_CONTROL_data|=(3<<0); // 1 atb_en_wei=1 write_16reg_data(lane0_RX_ANA_CONTROL_addr,lane0_RX_ANA_CONTROL_data); printk(KERN_ALERT "\n01.lane0_RX_ANA_CONTROL_data=0x%xh\n \n",lane0_RX_ANA_CONTROL_data); lane0_RX_ANA_CONTROL_data=read_16reg_data(lane0_RX_ANA_CONTROL_addr); printk(KERN_ALERT "\n1.lane0_RX_ANA_CONTROL_data=0x%xh\n \n",lane0_RX_ANA_CONTROL_data); //2.set dac_mode clock_DAC_CTL_data=read_16reg_data(clock_DAC_CTL_addr); clock_DAC_CTL_data&=~(7<<12); // dac_mode=12 clock_DAC_CTL_data|=(4<<12); // 100 write_16reg_data(clock_DAC_CTL_addr,clock_DAC_CTL_data); clock_DAC_CTL_data=read_16reg_data(clock_DAC_CTL_addr); printk(KERN_ALERT "\n2.clock_DAC_CTL_data=0x%xh\n \n",clock_DAC_CTL_data); //3. Write dac_chop atb_s_p connect to DAC , clock_RTUNE_CTL_data=read_16reg_data(clock_RTUNE_CTL_addr); clock_RTUNE_CTL_data&=~(0b1010011<<0); // clock_RTUNE_CTL_data|=(0b1000000<<0); // write_16reg_data(clock_RTUNE_CTL_addr,clock_RTUNE_CTL_data); clock_RTUNE_CTL_data=read_16reg_data(clock_RTUNE_CTL_addr); printk(KERN_ALERT "\n3.clock_RTUNE_CTL_data=0x%xh \n\n",clock_RTUNE_CTL_data); //4.0 set lane0.tx_ana.atbsel2.atb_en to 1 lane0_TX_ANA_ATBSEL2_data=read_16reg_data(lane0_TX_ANA_ATBSEL2_addr); lane0_TX_ANA_ATBSEL2_data|=(1<<7); // atb_en 1 write_16reg_data(lane0_TX_ANA_ATBSEL2_addr,lane0_TX_ANA_ATBSEL2_data); lane0_TX_ANA_ATBSEL2_data=read_16reg_data(lane0_TX_ANA_ATBSEL2_addr); printk(KERN_ALERT "\n4.0lane0_TX_ANA_ATBSEL2_data=0x%xh \n\n",lane0_TX_ANA_ATBSEL2_data); //4. tx_m connect to atb_s_p , lane0_TX_ANA_ATBSEL1_data=read_16reg_data(lane0_TX_ANA_ATBSEL1_addr); lane0_TX_ANA_ATBSEL1_data&=~(0x00ff); // lane0_TX_ANA_ATBSEL1_data|=(1<<4); // txp_s_p 1 write_16reg_data(lane0_TX_ANA_ATBSEL1_addr,lane0_TX_ANA_ATBSEL1_data); lane0_TX_ANA_ATBSEL1_data=read_16reg_data(lane0_TX_ANA_ATBSEL1_addr); printk(KERN_ALERT "\n4.lane0_TX_ANA_ATBSEL1_data=0x%xh \n\n",lane0_TX_ANA_ATBSEL1_data); //5.write DAC data clock_DAC_CTL_data=read_16reg_data(clock_DAC_CTL_addr); clock_DAC_CTL_data&=~(0x01ff); // clock_DAC_CTL_data|=(xx2<<0); // write_16reg_data(clock_DAC_CTL_addr,clock_DAC_CTL_data); clock_DAC_CTL_data=read_16reg_data(clock_DAC_CTL_addr); printk(KERN_ALERT "\n5.clock_DAC_CTL_data=0x%xh\n \n",clock_DAC_CTL_data); printk(KERN_ALERT " drv this is write_inter_DAC end \n"); return 0; } //all the reg can be read and write rightly,But the Txm allways be 0 voltage. What worrng with me,Looking forward to your help .thanks.
my email: ouzhenchao2012@163.com
