How to use i.MX8mm sai multi lane

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How to use i.MX8mm sai multi lane

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Contributor I

Hello,

I am using i.MX8MMINILPD4 EVK to verify audio related requirements. We plan to connect four TI audio chips on SAI1, three of which are ADC chips connected to the microphone and one DAC chip to connect the speakers. This requires four I2S channels, three of which are derived from the data collected by the microphone and the other is downlinked to the speaker. However, when SAI1 is configured in DTS and only one channel MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 is used, it can be used normally, but when the data is switched to MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2, it will not work. Is it necessary to configure another configuration to switch to MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2?


In addition, if I want three ADCs to be configured on the MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0, MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1, MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 three channels at the same time?


I have not found the answer in the i.MX 8M Mini Applications Processor Reference Manual, Rev. 1, 03/2019. If you have other references, you can share it with me.

Thank you!

Waye

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NXP TechSupport
NXP TechSupport

Hi Waye

for sai multi lane example one can look at pinctrl_sai1 :

fsl-imx8mm-evk.dts\freescale\dts\boot\arm64\arch - linux-imx - i.MX Linux kernel 

> if I want three ADCs to be configured on the MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0,

>MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1, MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2

>three channels at the same time?

yes

Best regards
igor
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Contributor I

Hi igor,

 

Thank you for your reply.

Yes, SAI1 RXD0 DATA0 line work.

But now I want to use SAI1 RXD2 DATA2.

So I modify fsl-imx8mm-evk.dts 

MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 to MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2.

And TI ADC3101 OUT connect PAD SAI1_RXD2.

Now it not work, do you have any suggestion?

BRs,

Waye

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NXP TechSupport
NXP TechSupport

Hi Waye

in &sai1.. one can try to remove "sai-multi-lane" parameter.

Best regards
igor

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Contributor I

Hi igor,

I tried to restore SAI1 RXD0 DATA0 and removed "fsl, sai-multi-lane" in fsl-imx8mm-evk.dts.

The original work of SAI1 RXD0 DATA0 is not working now.
Are you sure that deleting "fsl, sai-multi-lane" will not affect the work of SAI1?

Thanks,

Waye

 

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NXP TechSupport
NXP TechSupport

Hi Waye

one can debug in sai driver

fsl_sai.c\fsl\soc\sound - linux-imx - i.MX Linux kernel 

Pay attention to sect.13.9.3.5.4 FIFO Combine i.MX8M Mini Reference Manual:
"FIFO combining mode allows the separate FIFOs for multiple data channels to be used as
a single FIFO for either software accesses or a single data channel or both. Note that the
enabled data channels must be contiguous and data channel 0 must be enabled when
FIFO Combine mode is enabled."

Best regards
igor

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Contributor I

Hi igor,

I remove "fsl,sai-multi-lane;" and modify "MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2."

When tinycap a wav from sound card, the system will hang sevral seconds and reboot.

The wav file can not be saved and there haven't any logs output.

 

Do you have any more suggestion?

Thanks,

waye

********************************************************

&sai1 {
pinctrl-names = "default", "dsd";
pinctrl-0 = <&pinctrl_sai1>;
pinctrl-1 = <&pinctrl_sai1_dsd>;
assigned-clocks = <&clk IMX8MM_CLK_SAI1_SRC>,
<&clk IMX8MM_CLK_SAI1_DIV>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <0>, <49152000>;
clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_SAI1_ROOT>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>,
<&clk IMX8MM_AUDIO_PLL2_OUT>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
/*
fsl,sai-multi-lane;
*/
fsl,dataline,dsd = <0 0xff 0xff 2 0xff 0x11>;
dmas = <&sdma2 0 26 0>, <&sdma2 1 26 0>;
status = "okay";
};

pinctrl_sai1: sai1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6
MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6
MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6
MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6
MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6
MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6
MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6
MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6
MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6
MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0xd6
>;
};

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