Dear,
We designed a carrier board with i.MX6Q. And then the board includes M240HTN01.2.
So I modified DT, and I'm writing code below. But it isn't working! I think my DT isn't correct, and I have some questions.
Please advice for me.
1. When I check fb information using fbset command, V Hz is too fast.
# D: 142.410 MHz, H: 135.628 kHz, V: 120.025 Hz
2. I'm not sure the values of V/H Back porch, V/H Front porch and V/H Sync.
- My DT -
17 &mxcfb1 {
18 interface_pix_fmt = "RGB24";
19 };
32 &ldb {
33 split-mode;
34 status = "okay";
35
36 lvds-channel@0 {
37 fsl,data-mapping = "spwg";
38 fsl,data-width = <24>;
39 //crtc = "ipu1-di0";
40 crtc = "ipu1-di0";
41 status = "okay";
42 primary;
43
44 display-timings {
45 native-mode = <&timing0>;
46 timing0: hsd100pxn1 {
47 clock-frequency = <142400000>;
48 hactive = <960>;
49 vactive = <1080>;
50 hback-porch = <44>;
51 hfront-porch = <44>;
52 vback-porch = <24>;
53 vfront-porch = <24>;
54 hsync-len = <2>;
55 vsync-len = <2>;
56 };
57 };
58 };
60 lvds-channel@1 {
61 fsl,data-mapping = "spwg";
62 fsl,data-width = <24>;
63 crtc = "ipu1-di1";
64 status = "okay";
65
66 display-timings {
67 native-mode = <&timing1>;
68 timing1: hsd100pxn1 {
69 clock-frequency = <142400000>;
70 hactive = <960>;
71 vactive = <1080>;
72 hback-porch = <44>;
73 hfront-porch = <44>;
74 vback-porch = <24>;
75 vfront-porch = <24>;
76 hsync-len = <2>;
77 vsync-len = <2>;
78 };
79 };
80 };
115 mxcfb1: fb@0 {
116 compatible = "fsl,mxc_sdc_fb";
117 disp_dev = "ldb";
118 default_bpp = <24>;
119 int_clk = <0>;
120 late_init = <0>;
121 status = "disabled";
122 };
148 &mxcfb1 {
149 status = "okay";
150 };
151 /*
152 &mxcfb2 {
153 status = "okay";
154 };
155
156 &mxcfb3 {
157 status = "okay";
158 };
159
160 &mxcfb4 {
161 status = "okay";
162 };
163 */
- fbset command -
root@linaro-alip:~# fbset
mode "960x1080-120"
# D: 142.410 MHz, H: 135.628 kHz, V: 120.025 Hz
geometry 960 1080 960 1088 32
timings 7022 44 44 24 24 2 2
rgba 8/16,8/8,8/0,8/24
endmode
