I want to use DDR_Stress_Tester_V1.0.3 for imx6 sabresd(imx6dl, 2GB RAM, chip is H5TQ4G63MFR-PBC x 4).
“DDR_Stress_Tester -t mx6x -df mx6x_ddr_script_filename”
Which script file should I use?
MX6DL_ARD_DDR3_register_programming_aid_v0.2.inc or
MX6DL_SabreSD_DDR3_register_programming_aid_v1.5.inc?
Hi jiang
for sabresd one needs to use *SabreSD* file.
If you are testing own custom board - then script aid on link below
Best regards
igor
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Thank you for your reply.
I got the following result.
It means there are something wrong with memory?
And I think I need to update flash_header.S(uboot-imx) according to the output results,
but there is no explanation for this in User Guide.
How should I update flash_header.S based on the output?
-------------------------------------
P:\DDR_Stress_Tester_V1.0.3\Binary>DDR_Stress_Tester -t mx6x -df MX6DL_SabreSD_D
DR3_register_programming_aid_v1.5.inc
MX6DL opened.
HAB_TYPE: DEVELOP
Image loading...
download Image to IRAM OK
Re-open MX6x device.
Running DDR test..., press "ESC" key to exit.
******************************
DDR Stress Test (1.0.3) for MX6DL
Build: Jun 25 2014, 12:09:29
Freescale Semiconductor, Inc.
******************************
=======DDR configuration==========
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is DDR3
Data width: 64, bank num: 8
Row size: 14, col size: 10
Chip select CSD0 is used
Density per chip select: 1024MB
==================================
What ARM core speed would you like to run?
Type 0 for 650MHz, 1 for 800MHz, 2 for 1GHz
ARM set to 1GHz
Please select the DDR density per chip select (in bytes) on the board
Type 0 for 2GB; 1 for 1GB; 2 for 512MB; 3 for 256MB; 4 for 128MB; 5 for 64MB; 6
for 32MB
For maximum supported density (4GB), we can only access up to 3.75GB. Type 9 to
select this
DDR density selected (MB): 2048
Calibration will run at DDR frequency 400MHz. Type 'y' to continue.
If you want to run at other DDR frequency. Type 'n'
DDR Freq: 396 MHz
Would you like to run the write leveling calibration? (y/n)
Please enter the MR1 value on the initilization script
This will be re-programmed into MR1 after write leveling calibration
Enter as a 4-digit HEX value, example 0004, then hit enter
0004 You have entered: 0x0004
Start write leveling calibration
Write leveling calibration completed
MMDC_MPWLDECTRL0 ch0 after write level cal: 0x003B003F
MMDC_MPWLDECTRL1 ch0 after write level cal: 0x00320033
MMDC_MPWLDECTRL0 ch1 after write level cal: 0x0011001C
MMDC_MPWLDECTRL1 ch1 after write level cal: 0x00140022
Would you like to run the DQS gating, read/write delay calibration? (y/n)
Starting DQS gating calibration...
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BYTE 0:
Start: HC=0x00 ABS=0x30
End: HC=0x03 ABS=0x6C
Mean: HC=0x02 ABS=0x0E
End-0.5*tCK: HC=0x02 ABS=0x6C
Final: HC=0x02 ABS=0x6C
BYTE 1:
Start: HC=0x01 ABS=0x2C
End: HC=0x03 ABS=0x6C
Mean: HC=0x02 ABS=0x4C
End-0.5*tCK: HC=0x02 ABS=0x6C
Final: HC=0x02 ABS=0x6C
BYTE 2:
Start: HC=0x00 ABS=0x2C
End: HC=0x03 ABS=0x5C
Mean: HC=0x02 ABS=0x04
End-0.5*tCK: HC=0x02 ABS=0x5C
Final: HC=0x02 ABS=0x5C
BYTE 3:
Start: HC=0x00 ABS=0x28
End: HC=0x03 ABS=0x5C
Mean: HC=0x02 ABS=0x02
End-0.5*tCK: HC=0x02 ABS=0x5C
Final: HC=0x02 ABS=0x5C
BYTE 4:
Start: HC=0x01 ABS=0x10
End: HC=0x03 ABS=0x58
Mean: HC=0x02 ABS=0x34
End-0.5*tCK: HC=0x02 ABS=0x58
Final: HC=0x02 ABS=0x58
BYTE 5:
Start: HC=0x01 ABS=0x0C
End: HC=0x03 ABS=0x54
Mean: HC=0x02 ABS=0x30
End-0.5*tCK: HC=0x02 ABS=0x54
Final: HC=0x02 ABS=0x54
BYTE 6:
Start: HC=0x01 ABS=0x04
End: HC=0x03 ABS=0x4C
Mean: HC=0x02 ABS=0x28
End-0.5*tCK: HC=0x02 ABS=0x4C
Final: HC=0x02 ABS=0x4C
BYTE 7:
Start: HC=0x01 ABS=0x00
End: HC=0x03 ABS=0x40
Mean: HC=0x02 ABS=0x20
End-0.5*tCK: HC=0x02 ABS=0x40
Final: HC=0x02 ABS=0x40
DQS calibration MMDC0 MPDGCTRL0 = 0x426C026C, MPDGCTRL1 = 0x025C025C
DQS calibration MMDC1 MPDGCTRL0 = 0x42540258, MPDGCTRL1 = 0x0240024C
Note: Array result[] holds the DRAM test result of each byte.
0: test pass. 1: test fail
4 bits respresent the result of 1 byte.
result 00000001:byte 0 fail.
result 00000011:byte 0, 1 fail.
Starting Read calibration...
ABS_OFFSET=0x00000000 result[00]=0x11111111
ABS_OFFSET=0x04040404 result[01]=0x11111111
ABS_OFFSET=0x08080808 result[02]=0x11111111
ABS_OFFSET=0x0C0C0C0C result[03]=0x11111111
ABS_OFFSET=0x10101010 result[04]=0x11111111
ABS_OFFSET=0x14141414 result[05]=0x11111111
ABS_OFFSET=0x18181818 result[06]=0x11111011
ABS_OFFSET=0x1C1C1C1C result[07]=0x01100011
ABS_OFFSET=0x20202020 result[08]=0x00100010
ABS_OFFSET=0x24242424 result[09]=0x00000000
ABS_OFFSET=0x28282828 result[0A]=0x00000000
ABS_OFFSET=0x2C2C2C2C result[0B]=0x00000000
ABS_OFFSET=0x30303030 result[0C]=0x00000000
ABS_OFFSET=0x34343434 result[0D]=0x00000000
ABS_OFFSET=0x38383838 result[0E]=0x00000000
ABS_OFFSET=0x3C3C3C3C result[0F]=0x00000000
ABS_OFFSET=0x40404040 result[10]=0x00000000
ABS_OFFSET=0x44444444 result[11]=0x00000000
ABS_OFFSET=0x48484848 result[12]=0x00000000
ABS_OFFSET=0x4C4C4C4C result[13]=0x00000000
ABS_OFFSET=0x50505050 result[14]=0x00000000
ABS_OFFSET=0x54545454 result[15]=0x00000000
ABS_OFFSET=0x58585858 result[16]=0x00000000
ABS_OFFSET=0x5C5C5C5C result[17]=0x00000000
ABS_OFFSET=0x60606060 result[18]=0x00000000
ABS_OFFSET=0x64646464 result[19]=0x00000000
ABS_OFFSET=0x68686868 result[1A]=0x00000000
ABS_OFFSET=0x6C6C6C6C result[1B]=0x10000000
ABS_OFFSET=0x70707070 result[1C]=0x11001100
ABS_OFFSET=0x74747474 result[1D]=0x11001100
ABS_OFFSET=0x78787878 result[1E]=0x11111111
ABS_OFFSET=0x7C7C7C7C result[1F]=0x11111111
MMDC0 MPRDDLCTL = 0x44424C4A, MMDC1 MPRDDLCTL = 0x42464C48
Starting Write calibration...
ABS_OFFSET=0x00000000 result[00]=0x10101100
ABS_OFFSET=0x04040404 result[01]=0x10001000
ABS_OFFSET=0x08080808 result[02]=0x10001000
ABS_OFFSET=0x0C0C0C0C result[03]=0x00000000
ABS_OFFSET=0x10101010 result[04]=0x00000000
ABS_OFFSET=0x14141414 result[05]=0x00000000
ABS_OFFSET=0x18181818 result[06]=0x00000000
ABS_OFFSET=0x1C1C1C1C result[07]=0x00000000
ABS_OFFSET=0x20202020 result[08]=0x00000000
ABS_OFFSET=0x24242424 result[09]=0x00000000
ABS_OFFSET=0x28282828 result[0A]=0x00000000
ABS_OFFSET=0x2C2C2C2C result[0B]=0x00000000
ABS_OFFSET=0x30303030 result[0C]=0x00000000
ABS_OFFSET=0x34343434 result[0D]=0x00000000
ABS_OFFSET=0x38383838 result[0E]=0x00000000
ABS_OFFSET=0x3C3C3C3C result[0F]=0x00000000
ABS_OFFSET=0x40404040 result[10]=0x00000000
ABS_OFFSET=0x44444444 result[11]=0x00000000
ABS_OFFSET=0x48484848 result[12]=0x00000000
ABS_OFFSET=0x4C4C4C4C result[13]=0x00000000
ABS_OFFSET=0x50505050 result[14]=0x00000010
ABS_OFFSET=0x54545454 result[15]=0x00000010
ABS_OFFSET=0x58585858 result[16]=0x00010010
ABS_OFFSET=0x5C5C5C5C result[17]=0x00010010
ABS_OFFSET=0x60606060 result[18]=0x01110011
ABS_OFFSET=0x64646464 result[19]=0x11110011
ABS_OFFSET=0x68686868 result[1A]=0x11111111
ABS_OFFSET=0x6C6C6C6C result[1B]=0x11111111
ABS_OFFSET=0x70707070 result[1C]=0x11111111
ABS_OFFSET=0x74747474 result[1D]=0x11111111
ABS_OFFSET=0x78787878 result[1E]=0x11111111
ABS_OFFSET=0x7C7C7C7C result[1F]=0x11111111
MMDC0 MPWRDLCTL = 0x3834262E,MMDC1 MPWRDLCTL = 0x362E302A
MMDC registers updated from calibration
Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x426C026C
MPDGCTRL1 PHY0 (0x021b0840) = 0x025C025C
MPDGCTRL0 PHY1 (0x021b483c) = 0x42540258
MPDGCTRL1 PHY1 (0x021b4840) = 0x0240024C
Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x44424C4A
MPRDDLCTL PHY1 (0x021b4848) = 0x42464C48
Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x3834262E
MPWRDLCTL PHY1 (0x021b4850) = 0x362E302A
The DDR stress test can run with an incrementing frequency or at a static freq
To run at a static freq, simply set the start freq and end freq to the same valu
e
Would you like to run the DDR Stress Test (y/n)?
Enter desired START freq (135 to 672 MHz), then hit enter.
Note: DDR3 minimum is ~333MHz, do not recommend to go too much below this.
528
The freq you entered was: 528
Enter desired END freq (135 to 672 MHz), then hit enter.
Make sure this is equal to or greater than start freq
550
The freq you entered was: 550
Beginning stress test
loop: 1
DDR Freq: 528 MHz
t0.1: data is addr test
Address of failure: 0x50000000
Data was: 0x4fff00c0
But pattern should match address
if you are using custom board, you should not
use DDR3_register_programming_aid_v1.5.inc.
Instead one needs to create custom *.inc file
for your memory - "chip is H5TQ4G63MFR-PBC x 4",
based on results https://community.freescale.com/docs/DOC-94917
Hi Igor,
I am using DDR_Stress_Tester_V1.0.3_20_08_2014 for checking DDR3 for one of the non-booting i.MX6Q based custom board.
And I am getting below mentioned output for DDR stress test.
loop: 1
DDR Freq: 528 MHz
t0.1: data is addr test
Address of failure: 0x10000000
Data was: 0x00000000
But pattern should match address
Its seems there is an issue in RAM.
But I am not able conclude that whether the issue in data line or in address lines.
I would like to know whether its possible to identify data lines/address line issue using DDR Stress Tester?
Thank u very much!
I refered to the data sheet of memory chip and https://community.freescale.com/docs/DOC-94917,
got the result as follow.
And I think I need to update flash_header.S(uboot-imx) according to the output results,
but there is no explanation for this in User Guide.
How should I update flash_header.S based on the output?
-----------
Would you like to run the write leveling calibration? (y/n)
Please enter the MR1 value on the initilization script
This will be re-programmed into MR1 after write leveling calibration
Enter as a 4-digit HEX value, example 0004, then hit enter
0004 You have entered: 0x0004
Start write leveling calibration
Write leveling calibration completed
MMDC_MPWLDECTRL0 ch0 after write level cal: 0x00360039
MMDC_MPWLDECTRL1 ch0 after write level cal: 0x002D0034
MMDC_MPWLDECTRL0 ch1 after write level cal: 0x000E0017
MMDC_MPWLDECTRL1 ch1 after write level cal: 0x00110023
Would you like to run the DQS gating, read/write delay calibration? (y/n)
Starting DQS gating calibration...
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BYTE 0:
Start: HC=0x01 ABS=0x34
End: HC=0x03 ABS=0x70
Mean: HC=0x02 ABS=0x52
End-0.5*tCK: HC=0x02 ABS=0x70
Final: HC=0x02 ABS=0x70
BYTE 1:
Start: HC=0x01 ABS=0x3C
End: HC=0x03 ABS=0x74
Mean: HC=0x02 ABS=0x58
End-0.5*tCK: HC=0x02 ABS=0x74
Final: HC=0x02 ABS=0x74
BYTE 2:
Start: HC=0x00 ABS=0x28
End: HC=0x03 ABS=0x64
Mean: HC=0x02 ABS=0x06
End-0.5*tCK: HC=0x02 ABS=0x64
Final: HC=0x02 ABS=0x64
BYTE 3:
Start: HC=0x01 ABS=0x28
End: HC=0x03 ABS=0x64
Mean: HC=0x02 ABS=0x46
End-0.5*tCK: HC=0x02 ABS=0x64
Final: HC=0x02 ABS=0x64
BYTE 4:
Start: HC=0x00 ABS=0x1C
End: HC=0x03 ABS=0x5C
Mean: HC=0x01 ABS=0x7B
End-0.5*tCK: HC=0x02 ABS=0x5C
Final: HC=0x02 ABS=0x5C
BYTE 5:
Start: HC=0x01 ABS=0x10
End: HC=0x03 ABS=0x58
Mean: HC=0x02 ABS=0x34
End-0.5*tCK: HC=0x02 ABS=0x58
Final: HC=0x02 ABS=0x58
BYTE 6:
Start: HC=0x01 ABS=0x14
End: HC=0x03 ABS=0x4C
Mean: HC=0x02 ABS=0x30
End-0.5*tCK: HC=0x02 ABS=0x4C
Final: HC=0x02 ABS=0x4C
BYTE 7:
Start: HC=0x01 ABS=0x08
End: HC=0x03 ABS=0x40
Mean: HC=0x02 ABS=0x24
End-0.5*tCK: HC=0x02 ABS=0x40
Final: HC=0x02 ABS=0x40
DQS calibration MMDC0 MPDGCTRL0 = 0x02740270, MPDGCTRL1 = 0x02640264
DQS calibration MMDC1 MPDGCTRL0 = 0x0258025C, MPDGCTRL1 = 0x0240024C
Note: Array result[] holds the DRAM test result of each byte.
0: test pass. 1: test fail
4 bits respresent the result of 1 byte.
result 00000001:byte 0 fail.
result 00000011:byte 0, 1 fail.
Starting Read calibration...
ABS_OFFSET=0x00000000 result[00]=0x11111111
ABS_OFFSET=0x04040404 result[01]=0x11111111
ABS_OFFSET=0x08080808 result[02]=0x11111111
ABS_OFFSET=0x0C0C0C0C result[03]=0x11111111
ABS_OFFSET=0x10101010 result[04]=0x11111111
ABS_OFFSET=0x14141414 result[05]=0x11111111
ABS_OFFSET=0x18181818 result[06]=0x11111011
ABS_OFFSET=0x1C1C1C1C result[07]=0x11111011
ABS_OFFSET=0x20202020 result[08]=0x01100011
ABS_OFFSET=0x24242424 result[09]=0x00000010
ABS_OFFSET=0x28282828 result[0A]=0x00000000
ABS_OFFSET=0x2C2C2C2C result[0B]=0x00000000
ABS_OFFSET=0x30303030 result[0C]=0x00000000
ABS_OFFSET=0x34343434 result[0D]=0x00000000
ABS_OFFSET=0x38383838 result[0E]=0x00000000
ABS_OFFSET=0x3C3C3C3C result[0F]=0x00000000
ABS_OFFSET=0x40404040 result[10]=0x00000000
ABS_OFFSET=0x44444444 result[11]=0x00000000
ABS_OFFSET=0x48484848 result[12]=0x00000000
ABS_OFFSET=0x4C4C4C4C result[13]=0x00000000
ABS_OFFSET=0x50505050 result[14]=0x00000000
ABS_OFFSET=0x54545454 result[15]=0x00000000
ABS_OFFSET=0x58585858 result[16]=0x00000000
ABS_OFFSET=0x5C5C5C5C result[17]=0x00000000
ABS_OFFSET=0x60606060 result[18]=0x00000000
ABS_OFFSET=0x64646464 result[19]=0x00000000
ABS_OFFSET=0x68686868 result[1A]=0x00000000
ABS_OFFSET=0x6C6C6C6C result[1B]=0x00000000
ABS_OFFSET=0x70707070 result[1C]=0x00001000
ABS_OFFSET=0x74747474 result[1D]=0x10111111
ABS_OFFSET=0x78787878 result[1E]=0x11111111
ABS_OFFSET=0x7C7C7C7C result[1F]=0x11111111
MMDC0 MPRDDLCTL = 0x46444C4A, MMDC1 MPRDDLCTL = 0x484C4A48
Starting Write calibration...
ABS_OFFSET=0x00000000 result[00]=0x11101111
ABS_OFFSET=0x04040404 result[01]=0x11101001
ABS_OFFSET=0x08080808 result[02]=0x00001000
ABS_OFFSET=0x0C0C0C0C result[03]=0x00000000
ABS_OFFSET=0x10101010 result[04]=0x00000000
ABS_OFFSET=0x14141414 result[05]=0x00000000
ABS_OFFSET=0x18181818 result[06]=0x00000000
ABS_OFFSET=0x1C1C1C1C result[07]=0x00000000
ABS_OFFSET=0x20202020 result[08]=0x00000000
ABS_OFFSET=0x24242424 result[09]=0x00000000
ABS_OFFSET=0x28282828 result[0A]=0x00000000
ABS_OFFSET=0x2C2C2C2C result[0B]=0x00000000
ABS_OFFSET=0x30303030 result[0C]=0x00000000
ABS_OFFSET=0x34343434 result[0D]=0x00000000
ABS_OFFSET=0x38383838 result[0E]=0x00000000
ABS_OFFSET=0x3C3C3C3C result[0F]=0x00000000
ABS_OFFSET=0x40404040 result[10]=0x00000000
ABS_OFFSET=0x44444444 result[11]=0x00000000
ABS_OFFSET=0x48484848 result[12]=0x00000000
ABS_OFFSET=0x4C4C4C4C result[13]=0x00000000
ABS_OFFSET=0x50505050 result[14]=0x00000000
ABS_OFFSET=0x54545454 result[15]=0x00010000
ABS_OFFSET=0x58585858 result[16]=0x00010010
ABS_OFFSET=0x5C5C5C5C result[17]=0x00010010
ABS_OFFSET=0x60606060 result[18]=0x01010010
ABS_OFFSET=0x64646464 result[19]=0x01111110
ABS_OFFSET=0x68686868 result[1A]=0x11111110
ABS_OFFSET=0x6C6C6C6C result[1B]=0x11111111
ABS_OFFSET=0x70707070 result[1C]=0x11111111
ABS_OFFSET=0x74747474 result[1D]=0x11111111
ABS_OFFSET=0x78787878 result[1E]=0x11111111
ABS_OFFSET=0x7C7C7C7C result[1F]=0x11111111
MMDC0 MPWRDLCTL = 0x36322C38,MMDC1 MPWRDLCTL = 0x36323428
MMDC registers updated from calibration
Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x02740270
MPDGCTRL1 PHY0 (0x021b0840) = 0x02640264
MPDGCTRL0 PHY1 (0x021b483c) = 0x0258025C
MPDGCTRL1 PHY1 (0x021b4840) = 0x0240024C
Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x46444C4A
MPRDDLCTL PHY1 (0x021b4848) = 0x484C4A48
Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x36322C38
MPWRDLCTL PHY1 (0x021b4850) = 0x36323428
-----------