How to take the Uart3 on the expension connector into use from Cortex-M7 on i.MX8MPlus EVK

Z2025121 · ‎12-07-2023

How to change the uart port from Uart4 to Uart3 in the mcuxpresso SDK uart examples.

Board: i.MX8MPlus EVK

mcuxpresso SDK: 2.14.0

The default port for the uart examples are always UART4. We wanted to use the UART3 on the expansion connector from the Cortex-M7. We did the following adaptions but no signals comes out of Uart3 on the expansion connector.

Question I:

Do we need any other changes to get it work?

What we have done: we took one Uart example and changed the UART4 in the following lines (in (1) ...(5)) to Uart3:

(1) #define DEMO_UART UART4

(2) Clock

board.h:26: CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / (CLOCK_GetRootPreDivider(kCLOCK_RootUart4)) / \

board.h:27: (CLOCK_GetRootPostDivider(kCLOCK_RootUart4)) / 10

(3) IRQ

board.h:28:#define BOARD_UART_IRQ UART4_IRQn

board.h:29:#define BOARD_UART_IRQ_HANDLER UART4_IRQHandler

(4) clock configuration (According to the processor document, it seems that the Uart3 can use the same clock source as Uart4)

clock_config.c:105: CLOCK_SetRootMux(kCLOCK_RootUart4, kCLOCK_UartRootmuxSysPll1Div10); /* Set UART source to SysPLL1 Div10 80MHZ */

clock_config.c:106: CLOCK_SetRootDivider(kCLOCK_RootUart4, 1U, 1U);

(5) pinmux

pin_mux.c:58: IOMUXC_SetPinMux(IOMUXC_UART4_RXD_UART4_RX, 0U);

pin_mux.c:59: IOMUXC_SetPinConfig(IOMUXC_UART4_RXD_UART4_RX,

pin_mux.c:62: IOMUXC_SetPinMux(IOMUXC_UART4_TXD_UART4_TX, 0U);

pin_mux.c:63: IOMUXC_SetPinConfig(IOMUXC_UART4_TXD_UART4_TX, ...)

Question II:

There is a yaml section in the pin_mux.c (generated from PinMux Tools). Will they be used in building the Uart driver?

pin_mux.c:46: - {pin_num: AJ5, peripheral: UART4, signal: uart_rx, pin_signal: UART4_RXD, PE: Enabled, HYS: CMOS, PUE: Weak_Pull_Up, FSEL: Slow, DSE: X1}

pin_mux.c:47: - {pin_num: AH5, peripheral: UART4, signal: uart_tx, pin_signal: UART4_TXD, PE: Enabled, HYS: CMOS, PUE: Weak_Pull_Up, FSEL: Slow, DSE: X1}

If this is the case, does it mean the pin_mux.c has to be regenerated by adding Uart3?

Do you have any examples pin_mux.c where Uart3 is configured?

Many thanks and best regards

Chavira · ‎12-07-2023

Hi @Z2025121 !

Thank you for contacting NXP Support!

You have to configure the UART3 on "imx8mp_bl31_setup.c" of the ATF.

Please add the line "RDC_PDAPn(RDC_PDAP_UART2, D1R | D1W)" to declare the UART3 on the M core domain.

https://github.com/nxp-imx/imx-atf/blob/lf_v2.6/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c#L138

https://github.com/nxp-imx/imx-atf/blob/lf_v2.6/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c#L76

If you want to use Linux and the M core you should remove from the device tree the UART3

https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/arch/arm64/boot/dts/freescale/imx8mp-evk.dts#L954

Best Regards!

Alejandro

Z2025121 · ‎12-07-2023

Hi Alejandro,

Thanks for the hint for the Linux case for A-core. But we looking for Uart3 configuration in mcuxpresso SDK for Cortex-M7.

Uart3 on the expansion connector is routed to AC20 UART3_TXD, AF20 UART3_RXD. We have generated the pin_mux by using the online pin tool.

/***********************************************************************************************************************

* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file

* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.

**********************************************************************************************************************/

/*

* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************

!!GlobalInfo

product: Pins v14.0

processor: MIMX8ML8xxxLZ

package_id: MIMX8ML8DVNLZ

mcu_data: ksdk2_0

processor_version: 14.0.1

external_user_signals: {}

* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********

*/

#include "fsl_common.h"

#include "fsl_iomuxc.h"

#include "pin_mux.h"

/* FUNCTION ************************************************************************************************************

*

* Function Name : BOARD_InitBootPins

* Description : Calls initialization functions.

*

* END ****************************************************************************************************************/

void BOARD_InitBootPins(void)

{

}

/*

* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************

BOARD_InitPins:

- options: {callFromInitBoot: 'false', coreID: cm7, fullInit: 'true'}

- pin_list:

- {pin_num: AC20, peripheral: UART3, signal: uart_tx, pin_signal: ECSPI1_MOSI, PE: Enabled, HYS: CMOS, PUE: Weak_Pull_Up, ODE: Open_Drain_Disable, FSEL: Slow, DSE: X1,

SION: DISABLED}

- {pin_num: AF20, peripheral: UART3, signal: uart_rx, pin_signal: ECSPI1_SCLK, PE: Enabled, HYS: CMOS, PUE: Weak_Pull_Up, ODE: Open_Drain_Disable, FSEL: Slow, DSE: X1,

SION: DISABLED}

* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********

*/

/* FUNCTION ************************************************************************************************************

*

* Function Name : BOARD_InitPins

* Description : Configures pin routing and optionally pin electrical features.

*

* END ****************************************************************************************************************/

void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M7F[cm7] */

IOMUXC_SetPinMux(IOMUXC_ECSPI1_MOSI_UART3_TX, 0U);

IOMUXC_SetPinConfig(IOMUXC_ECSPI1_MOSI_UART3_TX,

IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |

IOMUXC_SW_PAD_CTL_PAD_PE_MASK);

IOMUXC_SetPinMux(IOMUXC_ECSPI1_SCLK_UART3_RX, 0U);

IOMUXC_SetPinConfig(IOMUXC_ECSPI1_SCLK_UART3_RX,

IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |

IOMUXC_SW_PAD_CTL_PAD_PE_MASK);

}

/***********************************************************************************************************************

* EOF

**********************************************************************************************************************/

Question:

We are unsure if the settings in the YMAL part are correct when we use the same parameters as Uart4 for HYS, PUE, FSEL and DSE. Are these settings correct?

/*

* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************

BOARD_InitPins:

- options: {callFromInitBoot: 'false', coreID: cm7, fullInit: 'true'}

- pin_list:

- {pin_num: AC20, peripheral: UART3, signal: uart_tx, pin_signal: ECSPI1_MOSI, PE: Enabled, HYS: CMOS, PUE: Weak_Pull_Up, ODE: Open_Drain_Disable, FSEL: Slow, DSE: X1,

SION: DISABLED}

- {pin_num: AF20, peripheral: UART3, signal: uart_rx, pin_signal: ECSPI1_SCLK, PE: Enabled, HYS: CMOS, PUE: Weak_Pull_Up, ODE: Open_Drain_Disable, FSEL: Slow, DSE: X1,

SION: DISABLED}

* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********

*/

Chavira · ‎12-07-2023

Hi @Z2025121!

You have to declare the UART3 on the M Core domain by changing the bootloader (On the BL31 phase), if you don't change the BL31 the UART3 is only used by A core.

Please try to modify the ATF and then debug your M-core application.

Best Regards!

Chavira