How to switch control of LPSPI3 from the M-core to the A-core domain on i.MX8ULP

[charleshuang]

Hi NXP Team,

As title.
Our customer has requested to switch the control of LPSPI3 from the M-Core to the A-Core on iMX8ULP.
The pin definitions for LPSPI3 on our board are as follows.
How should we modify the code for the M33 and A35 respectively?

        PTC13 => LPSPI3_SIN
        PTC14 => LPSPI3_SOUT
        PTC15 => LPSPI3_SCK
        PTC16 => LPSPI3_PCS0
        PTC17 => LPSPI3_PCS1

BR

[Zhiming_Liu]

Hi @charleshuang 

Please refer SDK_2_15_000_EVK9-MIMX8ULP\boards\evk9mimx8ulp\driver_examples\sema42\ to test shared peripheral between A core and M core.

Best Regards
Zhiming

[charleshuang]

Hi @Zhiming_Liu ,

sema42 seems just implemented a semaphore-like mechanism using shared memory only.
I think our customer is asking about "how to control LPSPI3 on APD ?"
Could you provide the relevant implementation methods and directions?

[Zhiming_Liu]

Hi @charleshuang 

The clock of  LPSPI3 can only be controlled by RTD domain.It is highly unlikely that customers will be able to control LPSPI3 independently in the A35 domain.

The clocking scheme provides clear separation between Real Time Domain (RTD), Low Power Audio and Video (LPAV) domain
and Application Domain (AD). Except for a few clock sources shared between three domains, such as the System Oscillator clock,
and the Free Running Oscillator(FRO), clock sources and clock management are separated and contained within each domain.
RTD clock management consists of RTD _CGC, PCC0, PCC1, PCC2 and CMC0 modules.

Customer can only choose shared memory to let A35 access LPSPI3, can't realize peripherals mapping with PDAP( Peripheral Domain Access Permissions) between A35 and M33 domain because there is no such registers. There is only MBC registers about LPSPI3. I can't find spi-rpmsg driver in Linux kernel, so customer need write it.

If customer need to use LPSPI in A35, they should consider use LPSPI* in A35 domain.

Best Regards

Zhiming