How to set vsync-len for MIPI-DSI Host?

[huynhduchau]

Hello all

Does anyone know how to set DSI vsync-len value on IMX8MQ?

I've looked at chapter 13.6 in IMX8MQ Reference Manual (IMX8MDQLQRM), it seems only hsync-len can be set by  MIPI_DSI_HOST_DPI_INTFC_DSI_HOST_CFG_DPI_HSA register.

However, these MIPI-DSI parameters (hsync len, vsync len) can be found in IMX8MM reference manual ( 13.5.5.1.13). 

Thanks!

[joanxie]

you can set this in the dts file, for example：rm67191 

  display-timings {
   timing {
    clock-frequency = <132000000>;
    hactive = <1080>;
    vactive = <1920>;
    hfront-porch = <20>;
    hsync-len = <2>;
    hback-porch = <34>;
    vfront-porch = <10>;
    vsync-len = <5>;
    vback-porch = <4>;
    hsync-active = <0>;
    vsync-active = <0>;
    de-active = <0>;
    pixelclk-active = <0>;
   };
  };

[huynhduchau]

Thanks for hint.

But I believe vsync-len value won't be set to MIPI-DSI bridge.

Kernel driver lacks of setting vsync-len as I read from this code:

static void nwl_dsi_config_dpi(struct nwl_mipi_dsi *dsi)
{
struct device *dev = dsi->dev;
struct mipi_dsi_device *dsi_device = dsi->dsi_device;
struct videomode vm;
enum dpi_pixel_format pixel_format =
nwl_dsi_get_dpi_pixel_format(dsi_device->format);
enum dpi_interface_color_coding color_coding =
nwl_dsi_get_dpi_interface_color_coding(dsi_device->format);
bool burst_mode;

drm_display_mode_to_videomode(dsi->curr_mode, &vm);

nwl_dsi_write(dsi, INTERFACE_COLOR_CODING, color_coding);
nwl_dsi_write(dsi, PIXEL_FORMAT, pixel_format);
DRM_DEV_DEBUG_DRIVER(dev, "DSI format is: %d (CC=%d, PF=%d)\n",
dsi_device->format, color_coding, pixel_format);

/*TODO: need to make polarity configurable */
nwl_dsi_write(dsi, VSYNC_POLARITY, 0x00);
nwl_dsi_write(dsi, HSYNC_POLARITY, 0x00);

burst_mode = (dsi_device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) &&
!(dsi_device->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE);

if (burst_mode) {
nwl_dsi_write(dsi, VIDEO_MODE, 0x2);
nwl_dsi_write(dsi, PIXEL_FIFO_SEND_LEVEL, 256);
} else {
nwl_dsi_write(dsi, VIDEO_MODE, 0x0);
nwl_dsi_write(dsi, PIXEL_FIFO_SEND_LEVEL, vm.hactive);
}

nwl_dsi_write(dsi, HFP, vm.hfront_porch);
nwl_dsi_write(dsi, HBP, vm.hback_porch);
nwl_dsi_write(dsi, HSA, vm.hsync_len);

nwl_dsi_write(dsi, ENABLE_MULT_PKTS, 0x0);
nwl_dsi_write(dsi, BLLP_MODE, 0x1);
nwl_dsi_write(dsi, ENABLE_MULT_PKTS, 0x0);
nwl_dsi_write(dsi, USE_NULL_PKT_BLLP, 0x0);
nwl_dsi_write(dsi, VC, 0x0);

nwl_dsi_write(dsi, PIXEL_PAYLOAD_SIZE, vm.hactive);
nwl_dsi_write(dsi, VACTIVE, vm.vactive);
nwl_dsi_write(dsi, VBP, vm.vback_porch);
nwl_dsi_write(dsi, VFP, vm.vfront_porch);
}

Btw, I'm using LCDIF as source for the bridge, and LCDIF register values seem correct.

[joanxie]

yes, dsi bridge doesn't set this in the dts file, depends on what panel you use, you can add this in the dts file according to the panel you use