How to set iomux for GPIO operation?

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How to set iomux for GPIO operation?

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timellis
Contributor I

I'm trying to find a simple example of how to set the iomux in a kernel module to enable GPIO operation on a given pin.

For example, I want to use GPIO3_IO01. I see that it's ALT5 on the EIM_DA1 pad. I've found that the Pad Mux Register is IOMUXC_SW_MUX_CTL_PAD_EIM_AD01.

However, when I try to set this register with a writel(), I get an error that "Unable to handle kernel paging request at virtual address..."

Obviously I'm missing something in the way I am setting this up. Can someone please enlighten me with a simple example of code that would properly set the pad mux register to allow me to use the GPIO?

Thank you.

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This an automatic process.

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Tim

one can use functions gpio_request,gpio_direction_output, gpio_set_value

as in attached file. Also one can look at

FAQ All Boards GPIO Test

Best regards

igor

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timellis
Contributor I

I know all of that. My question is lower-level than that.

I'm talking about how do you set the registers to configure the pad to even be accessible as a GPIO instead of the other possible modes that each pad can be.

I figured out something that works, but I'm not entirely clear on the concept and would like to fully understand the proper way to do it. Here's the code I'm using to set GPIO3_IO09:

#include "iomux_register.h"

#define GPIO3_IO09 73

{

     void __iomem *eim_da9 = ioremap(IOMUXC_SW_MUX_CTL_PAD_EIM_DA9,28);

     writel(0x05,eim_da9);

     gpio_request(GPIO3_IO09,"gpio3-09");

     gpio_direction_output(GPIO3_IO09,0);

}


It's the ioremap and the writel part that I'm talking about.

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andrewdyer
Contributor III

I'm not sure ioremap is what you want.  The tools I've seen for this use mmap on /dev/mem

http://free-electrons.com/pub/mirror/devmem2.c

boundarydevices/devregs · GitHub

or the memtool that comes in the unit tests in a yocto release build

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igorpadykov
NXP TechSupport
NXP TechSupport

SION bit is used to configure the pad to even be accessible as a GPIO instead of the other possible modes

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