How to set i.MX6 IPU DI display size and active window.

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How to set i.MX6 IPU DI display size and active window.

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satoshishimoda
Senior Contributor I

Hi community,

I have some questions about i.MX6DL IPU setting.

[Q1]

Please see Figure 38-45 in IMX6SDLRM Rev.1.

I understand I can set "Display height (lines)" by DIx_SCREEN_HEIGHT field in IPU_DIx_SCR_CONF register.

Is my understanding correct?

[Q2]

How can I set "Display width (pixels or accesses)"?

[Q3]

I understand antive wildow resolution and LCD resolution are not necessarily the same.

If the LCD resolution is 1920 x 1080, I have to set "Display width (pixels or accesses)" = 1920 and "Display height (lines)" = 1080.

But I can set AW_HEND <= 1920 and AW_VEND <= 1080.

Is this correct?

Best Regards,

Satoshi Shimoda

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Yuri
NXP Employee
NXP Employee

The IPU DI provides display sync signals, corresponding waveforms,

where screen size parameters are (in some sense) “hardcoded” via DC microcodes

IPU_DIx_SCR_CONF register also should be set.

This is possible to configure active window size parameters less than actual
display sizes.

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Yuri
NXP Employee
NXP Employee

The IPU DI provides display sync signals, corresponding waveforms,

where screen size parameters are (in some sense) “hardcoded” via DC microcodes

IPU_DIx_SCR_CONF register also should be set.

This is possible to configure active window size parameters less than actual
display sizes.

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erickang
Contributor II

Dear Yuri,

I have a question for LCD configuration.

I can see the LCD Configuration values in include/linux/fb.h like as below,

<Linux>/include/linux/fb.h

struct fb_videomode {                         <CLAA-WVGA>

   const char *name; /* optional */          : "CLAA-WVGA"   : CLAA-WVGA   :

   u32 refresh;      /* optional */              : 57    : Refresh rate in Hz  : FV

   u32 xres;                                            : 800    : resolution in x  : HDISP

   u32 yres;                                            : 480    : resolution in y  : VDISP

   u32 pixclock;                                      : 37037    : Pixel clock in picoseconds :

   u32 left_margin;                                 : 40    : Horizontal Back Porch  : HBP

   u32 right_margin;                                 : 60    : Horizontal Front Porch : HFP

   u32 upper_margin;                            : 10    : Vertical Back Porch  : VBP

   u32 lower_margin;                            : 10    : Vertical Front Porch  : VFP

   u32 hsync_len;                                 : 20    : Hsync pulse width  :

   u32 vsync_len;                                 : 10    : Vsync pulse width  :

   u32 sync;                                            : FB_SYNC_CLK_LAT_FALL  : Polarity on the Data Enable :

   u32 vmode;                                       : FB_VMODE_NONINTERLACED : Video Mode   :

   u32 flag;                                            : 0    : 0    :

};

Could you tell me what register was configured for each values of fb_videomode?

Best Regards,

Eric.

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Yuri
NXP Employee
NXP Employee

Linux documentation for i.MX6 does not contain recommendations for LCD using / adaptation.

I think we can use Chapter 18 (Supporting the i.MX53 Reference Board DISP0 LCD) of

i.MX53 System Development User’s Guide to clarify some aspects for i.MX6 too.

http://cache.freescale.com/files/32bit/doc/user_guide/MX53UG.pdf

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